6-Bit, 200 MSPS/500 MSPS TxDAC+® with 2×/4×/8× Interpolation and Signal Processing AD9786 FEATURES PRODUCT HIGHLIGHTS 16-bit resolution, 200 MSPS input data rate IMD 90 dBc @10 MHz Noise spectral density (NSD): −164 dBm/Hz @ 10 MHz WCDMA ACLR = 80 dBc @ 40 MHz IF DNL = ±0.3 LSB INL = ±0.
AD9786 TABLE OF CONTENTS Features .............................................................................................. 1 General Operation of the Serial Interface............................... 20 Applications....................................................................................... 1 Serial Interface Port Pin Descriptions ..................................... 20 Product Highlights ........................................................................... 1 MSB/LSB Transfers ...
AD9786 REVISION HISTORY 10/05—Rev. A to Rev. B Updated Format.................................................................. Universal Changes to Figure 1...........................................................................1 Changes to Table 2 ............................................................................6 Changes to Table 3 ............................................................................7 Changes to External Sync Mode Section .....................................
AD9786 GENERAL DESCRIPTION The AD9786 is a 16-bit, high speed, CMOS DAC with 2×/4×/8× interpolation and signal processing features tuned for communications applications. It offers state-of-the-art distortion and noise performance. The AD9786 was developed to meet the demanding performance requirements of multicarrier and third-generation base stations. The selectable interpolation filters simplify interfacing to a variety of input data rates while also taking advantage of oversampling performance gains.
AD9786 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA, unless otherwise noted. Table 1.
AD9786 DYNAMIC SPECIFICATIONS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA; differential transformer coupled output; 50 Ω doubly terminated, unless otherwise noted. Table 2.
AD9786 DIGITAL SPECIFICATIONS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance CLOCK INPUTS1 Input Voltage Range Common-Mode Voltage Differential Voltage Latch Pulse Width (tLPW) Data Setup Time to DACCLK Out in Master Mode (tS) Data Hold Time to DACCLK Out in Master Mode (tH) 1 Min Typ Max Unit 0 0.
AD9786 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD1, AVDD2, DRVDD ACVDD, ADVDD, CLKVDD, DVDD AGND1, AGND2, ACGND, ADGND, CLKGND, DGND REFIO, FSADJ IOUTA, IOUTB P1B15 to P1B0, P2B15 to P2B0, RESET DATACLK CLK+, CLK− CSB, SCLK, SDIO, SDO Junction Temperature Range Storage Temperature Lead Temperature (10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
AD9786 DNC ADVDD ADGND ACVDD ACGND AVDD2 AVDD1 AGND2 AGND1 IOUTA IOUTB AGND1 AVDD1 AGND2 AVDD2 ACGND ADGND ACVDD ADVDD DNC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CLKVDD 1 DNC 2 60 FSADJ PIN 1 IDENTIFIER 59 REFIO CLKVDD 3 58 RESET CLKGND 4 57 CSB CLK+ 5 56 SCLK CLK– 6 55 SDIO 54 SDO CLKGND 7 53 DGND DGND 8 DVDD 9 52 DVDD AD9786 P1B15 10 51 P2B0 TOP VIEW (Not to Scale) P1B14 11 50 P2B1 P1B13 12 49 P2B2
AD9786 ANALOG Table 7. Analog Pin Function Descriptions Pin No. 59 60 70, 71 61 62, 79 63, 78 64, 77 65, 76 66, 75 67, 74 68, 73 69, 72 80 Mnemonic REFIO FSADJ IOUTB, IOUTA DNC ADVDD ADGND ACVDD ACGND AVDD2 AGND2 AVDD1 AGND1 DNC Direction A A A Description Reference. Full-Scale Adjust. Differential DAC Output Currents. Do Not Connect. Analog Domain Digital Content 2.5 V. Analog Domain Digital Content 0 V. Analog Domain Clock Content 2.5 V. Analog Domain Clock Content 0 V. Analog Domain Clock Switching 3.
AD9786 SERIAL INTERFACE Table 9. Serial Interface Pin Function Descriptions Pin No. 54 Mnemonic SDO Direction O 55 SDIO I/O 56 57 58 SCLK CSB RESET I I I Description SDIODIR CSB 0x00[7] Mode 1 X High impedance. 0 0 Serial data output. 0 1 High impedance. SDIODIR CSB 0x00[7] Mode 1 X High impedance. 0 0 Serial data output. 0 1 Serial data input/output depending on Bit 7 of the serial instruction byte. Serial Interface Clock. Serial Interface Chip Select. Resets entire chip to default state. Rev.
AD9786 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.
AD9786 Group Delay Number of input clocks between an impulse applied at the device input and peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range Impulse Response Response of the device to an impulse applied to the input. Adjacent Channel Leakage Ratio (ACLR) A ratio in dBc between the measured power within a channel relative to its adjacent channel.
AD9786 TYPICAL PERFORMANCE CHARACTERISTICS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA; differential transformer coupled output; 50 Ω doubly terminated, unless otherwise noted. 120 120 100 100 –6dBFS –6dBFS 0dBFS 40 40 20 20 0 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 0dBFS 60 0 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 Figure 3. SFDR vs. Frequency, fDATA = 200 MSPS, 1× Interpolation Figure 6. SFDR vs.
AD9786 90 85 85 80 OUT OF BAND SFDR (dBc) 90 –3dBFS –6dBFS 70 0dBFS 65 60 0dBFS –3dBFS 75 70 –6dBFS 65 60 55 55 0 10 20 30 40 50 FOUT (MHz) 60 70 80 50 03152-009 50 0 10 20 30 ANALOG OUTPUT FREQUENCY (MHz) 03152-012 SFDR (dBc) 75 80 40 Figure 12. Out-of-Band SFDR, fDATA = 100 MSPS, 4× Interpolation Figure 9.
AD9786 100 100 95 95 –3dBFS –3dBFS 90 80 80 IMD (dBc) 85 75 0dBFS 70 65 60 55 55 20 40 60 80 100 FOUT (MHz) 120 140 160 Figure 15. Third-Order IMD vs. Frequency, fDATA = 160 MSPS, 2× Interpolation 0dBFS 70 60 0 50 0 20 40 60 FOUT (MHz) 80 100 Figure 18. Third-Order IMD vs.
AD9786 100 0.3 95 –3dBFS 0.2 90 0.1 85 –6dBFS DNL (LSBs) IMD (dBc) 80 75 70 0dBFS 65 0 –0.1 –0.2 60 –0.3 0 20 40 60 80 100 120 140 160 180 200 220 240 260 FOUT (MHz) –0.4 03152-021 50 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE Figure 24. Typical DNL Figure 21. Third-Order IMD vs. Frequency, fDATA = 62.5 MSPS, 8× Interpolation 1.25 –140 1.00 0.25 0 –0.50 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE 03152-022 –0.
AD9786 –150 –154 10 AIN = –3dBFS –156 Ref Lv1 10 dBm Marker 1 [T1] RBW 10 kHz RF Att 20 dB –87.73 dBm VBW 10 kHz 9.71442886 MHz SWT 5s Unit dBm A 0 –10 –158 –20 AIN = 0dBFS –160 1MA –30 1AVG –40 –162 –50 AIN = –6dBFS –164 –60 –70 –166 –80 –168 1 –90 –170 0 20 40 60 80 100 120 ANALOG OUTPUT FREQUENCY (MHz) 140 160 –100 03152-027 NOISE SPECTRAL DENSITY (dBm/Hz) –152 –110 START 100 kHz 19.9 MHz/ STOP 200 MHz Figure 30.
AD9786 REF –22.76dBm *AVG Log 10dB/ REF –33.3dBm *AVG Log 10dB/ *ATTEN 8dB *ATTEN 6dB AC-COUPLED AC-COUPLED AVERAGE 104 AVERAGE 22 PAVG 104 W1 S2 CENTER 46.40MHz *RES BW 30kHz VBW 300kHz RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz –10.38dBm/ 10.000MHz 3.84 MHz 15.000MHz 3.840MHz 3.840MHz 3.840MHz SPAN 33.84MHz SWEEP 109.8ms (601 pts) LOWER dBc dBm –79.00 –89.38 –80.78 –91.16 –79.71 –90.09 UPPER dBc dBm –79.63 –90.01 –81.77 –92.15 –81.45 –91.83 CARRIER POWER 5.000MHz –20.32dBm/ 10.
AD9786 SERIAL CONTROL INTERFACE Instruction Byte SDIO (PIN 55) SCLK (PIN 56) AD9786 SPI PORT INTERFACE CSB (PIN 57) 03152-036 SDO (PIN 54) Figure 36. AD9786 SPI Port Interface The AD9786 serial port is a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols.
AD9786 MSB/LSB TRANSFERS INSTRUCTION CYCLE A4 A3 The same considerations apply to setting the software reset SWRST (0x00[5]) bit. All other registers are set to their default values, but the software reset does not affect the bits in Register Address 0x00 and Register Address 0x04. A0 D7 D6N D5N D30 D20 D10 D00 D7 D6N D5N D30 D20 D10 D00 Figure 37.
AD9786 MODE CONTROL (VIA SERIAL PORT) Table 11.
AD9786 Table 14.
AD9786 Table 16.
AD9786 Table 20.
AD9786 DIGITAL FILTER SPECIFICATIONS DIGITAL INTERPOLATION FILTER COEFFICIENTS 0 Table 23. Stage 1 Interpolation Filter Coefficients Upper Coefficient H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) H(28) H(27) H(26) H(25) H(24) H(23) Integer Value 9 0 –27 0 65 0 –131 0 239 0 –407 0 665 0 –1070 0 1764 0 –3273 0 10358 16384 –20 –40 –60 –80 –100 –120 –140 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.
AD9786 CLOCK/DATA TIMING Table 26. Data Port Synchronization DCLKEXT 0x02, Bit 3 1 1 MODSYNC 0x05, Bit 3 0 1 DCLKCRC 0x02, Bit 2 X X Mode DATACLK Master Modulator Master 0 0 0 External Sync Mode 0 0 1 DATACLK Slave 0 1 0 Low Setup/Hold 0 1 1 Modulator Slave Two-Port Data Input Mode (DATACLK Master) With the interpolation set to 1×, the DATACLK output is a delayed and inverted version of DACCLK at the same frequency.
AD9786 Note that DCLKPOL (Register 0x02, Bit 4) can be used to select the edge of DACCLK upon which the input data is latched. DATACLKOUT There are three status bits available for a read that allow the user to verify DLL lock. These are Bit 0, Bit 1, and Bit 2 (DCRCSTAT) in Register 0x12. 03152-046 DACCLKIN There is a defined setup-and-hold window with respect to input data and the latching edge of DACCLK. There is also a required timing relationship between DATACLK and DACCLK.
AD9786 Low Setup/Hold Mode (DATACLK Input, Data Recovery Off) DACCLKIN Some applications might require that digital input data be synchronized with the DATACLK input, rather than DACCLK. For these applications, the AD9786 can be programmed for low setup/hold mode by entering the values in Table 26 into the SPI registers. With data recovery off and the MODSYNC bit set to Logic 1, the AD9786 latches data in upon the rising or falling edge of DATACLK input, depending on the state of DCLKPOL.
AD9786 Figure 54, Figure 55, and Figure 56 show the alignment for the latching edge of DACCLK with 4× interpolation and different settings for DATAADJ. In Figure 54, the AD9786 is in DATACLK master mode. DATAADJ is set to 0000, with DCLKPOL set to 0 so that the latching edge of DACCLK is immediately before the rising edge of DATACLK. The data transitions shown in Figure 54 are synchronous with the DACCLK, so that DACCLK and input data are constant with respect to each other.
AD9786 data images falling in the interpolation filter pass band are passed. In band-limited applications, the images at the output |of the DAC must be limited by an analog reconstruction filter. The complexity of the analog reconstruction filter is determined by the proximity of the closest image to the required signal band. Higher interpolation rates yield larger stop-band regions, suppressing more input images and resulting in a much relaxed analog reconstruction filter. Interpolation Modes Table 28.
AD9786 REAL AND COMPLEX SIGNALS A complex signal contains both magnitude and phase information. Given two signals at the same frequency, if the leading signal in phase is cosinusoidal and the lagging signal is sinusoidal, information pertaining to the magnitude and phase of a combination of the two signals can be derived; the combination of the two signals can be considered a complex signal.
AD9786 MODULATION MODES Table 30. Single-Channel Modulation MODDUAL 0 0 0 0 0 0 0 0 CHANNEL 0 0 0 0 1 1 1 1 MOD[1] 0 0 1 1 0 0 1 1 MOD[0] 0 1 0 1 0 1 0 1 Mode I channel, no modulation I channel, modulation by fDAC/2 I channel, modulation by fDAC/4 I channel, modulation by fDAC/8 Q channel, no modulation Q channel, modulation by fDAC/2 Q channel, modulation by fDAC/4 Q channel, modulation by fDAC/8 Either channel of the AD9786 interpolation filter channels can be routed to the DAC and modulated.
AD9786 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 fDAC fDAC/8 fDAC/8 0 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –7fDAC/8 –fDAC FILTERED INTERPOLATION IMAGES fDAC 03152-059 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –7fDAC/8 Figure 59.
AD9786 NO INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 0 –50 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 6 8 fSIN ×2 INTERPOLATION 0 INTERP[1] = 0 –50 INTERP[0] = 1 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 6 8 fSIN ×4 INTERPOLATION 0 INTERP[1] = 1 –50 INTERP[0] = 0 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 6 8 fSIN ×8 INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 1 –50 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 6 8 fSIN 03215-061 MOD[1] = 1 –100
AD9786 Table 33. Dual-Channel Complex Modulation MODDUAL 0 0 0 0 0 0 0 0 CHANNEL 0 0 0 0 1 1 1 1 MOD[1] 0 0 1 1 0 0 1 1 MOD[0] 0 1 0 1 0 1 0 1 Mode Real output, no modulation Real output, modulation by fDAC/2 Real output, modulation fDAC/4 Real output, modulation fDAC/8 Image output, no modulation Image output, modulation by fDAC/2 Image output, modulation by fDAC/4 Image output, modulation by fDAC/8 Table 34.
AD9786 ×2 INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 0 –100 –150 –8 MOD[0] = 1 –6 –4 –2 0 2 4 0 6 8f SIN ×4 INTERPOLATION INTERP[1] = 1 INTERP[0] = 0 –50 MOD[1] = 0 –100 –150 –8 MOD[0] = 1 –6 –4 –2 0 2 4 0 6 8f SIN ×8 INTERPOLATION INTERP[1] = 1 INTERP[0] = 1 –50 MOD[1] = 0 –100 –6 –4 –2 0 2 4 6 8f SIN 03152-064 –150 –8 MOD[0] = 1 Figure 64.
AD9786 POWER DISSIPATION 60 The AD9786 has seven power-supply domains: two 3.3 V analog domains (AVDD1 and AVDD2), two 2.5 V analog domains (ADVDD and ACVDD), one 2.5 V clock domain (CLKVDD), and two digital domains (DVDD, which runs from 2.5 V; and DRVDD, which runs from 3.3 V). 4× 2× 30 1× 20 10 0 0 25 50 75 100 125 150 FDATA (MSPS) 175 200 225 250 03152-068 The current for the 2.5 V analog supplies and the digital supplies varies depending on speed and mode of operation.
AD9786 fDAC 7fDAC/8 3fDAC/4 5fDAC/8 fDAC/2 3fDAC/8 fDAC/4 fDAC/8 0 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –fDAC –7fDAC/8 FILTERED INTERPOLATION IMAGES fDAC 7fDAC/8 3fDAC/4 5fDAC/8 fDAC/2 3fDAC/8 fDAC/4 fDAC/8 0 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –fDAC –7fDAC/8 fS/8 MODULATION fDAC 03152-070 7fDAC/8 3fDAC/4 5fDAC/8 fDAC/2 3fDAC/8 fDAC/4 fDAC/8 0 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –fDAC –7fDAC/8 fS/4 MODULATION
AD9786 Figure 72 shows this effect at the DAC output for a signal mirrored asymmetrically about dc that is produced by complex modulation without a Hilbert transform. The signal bandwidth was narrowed to show the aliased negative frequency interpolation images. The transfer function of an ideal Hilbert transform has a +90° phase shift for negative frequencies, and a –90° phase shift for positive frequencies. Because of the discontinuities that occur at 0 Hz and at 0.
AD9786 A baseband double sideband signal modulated to IF increases IF filter complexity and reduces power efficiency. If the baseband signal is complex, a single sideband IF modulation can be used, relaxing IF filter complexity and increasing power efficiency. 4 3 2 1 The AD9786 has the ability to place the baseband single sideband complex signal either above or below the IF frequency. Figure 78, Figure 79, and Figure 80 illustrate this.
AD9786 The second master mode, DATACLK master mode, generates a reference clock that is at the channel data rate. In this mode, the slave devices align their internal channel data rate clock to the master. If modulator phase alignment is needed, a concurrent serial write to all slave devices is necessary. To achieve this, the CSB pin on all slaves must be connected together, and a group serial write to the MODADJ register bits must be performed.
AD9786 DATADJ[3:0] 0000 1111 0001 DAC CLOCK RECEIVED CHANNEL DATA RATE CLOCK –1 03152-082 LOCAL CHANNEL DATA RATE CLOCK +1 Figure 82. Local Channel Data Rate Clock Synchronized with Offset STATE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DECODE 1 0 1/ 2 0 0 0 –1/ 2 0 –1 0 –1/ 2 0 0 0 –1/ 2 0 fs/8 0 0 0 2 3 4 1 5 6 2 7 03152-083 fs/4 fs/2 1 3 1 Figure 83.
AD9786 OPERATING THE AD9786 REV. F EVALUATION BOARD This section provides information to power up the board and verify correct operation; a description of more advanced modes of operation has been omitted. POWER SUPPLIES The AD9786 Rev. F evaluation board has five power supply connectors, labeled AVDD1, AVDD2, ACVDD/ADVDD, CLKVDD, and DVDD, whereas the AD9786 has seven power supply domains.
AD9786 DATA INPUTS ANALOG OUTPUT Digital data inputs to the AD9786 are accessed on the evaluation board through Connector J1 and Connector J2. These are 40-pin, right-angle connectors that are intended to be used with standard ribbon cable connectors. The input level should be 3.3 V. The data format is selectable through Register 0x02, Bit 7 (DATAFMT). With this bit set to a default 0, the AD9786 assumes that the input data is in twos complement format.
Rev. B | Page 46 of 56 Figure 87. Power Supply Distribution, Rev. F Evaluation Board 03152-087 S11 3.3VQ 2.5VQ CGND;3,4,5 SMAEDGE CLKVDD_IN 2 AGND; 3,4,5 SMAEDGE 1 S10 3.3V AGND2; 3,4,5 AVDD_IN S9 SMAEDGE 2.5VN DGND; 3,4,5 ADVDD3_IN S5 SMAEDGE 2.5V AGND2; 3,4,5 DVDD_IN S7 SMAEDGE ADVDD2_IN L2 FERRITE C65 22μF 16V TP6 RED TP4 RED TP2 RED TP18 BLK TP13 RED TP1 RED C69 0.1μF C68 0.1μF AVD1 C67 0.1μF C48 0.1μF C47 0.
Figure 88. AD9786 Local Circuitry, Rev. F Evaluation Board Rev. B | Page 47 of 56 IQ B A S6 1 2 3 DGND; 3,4,5 OPCLK_3 JP28 BD15 03152-088 TP14 WHT C33 0.1μF OPCLK JP27 BD14 + C7 10μF 6.3V DVDD + C8 10μF 6.3V DVDD + C9 10μF 6.3V DVDD OPCLK S4 DATACLK S2 C54 0.001μF DGND; 3,4,5 + C31 10μF 6.3V DRVDD + C10 10μF 6.3V C26 0.001μF C23 0.001μF C24 0.001μF C25 0.001μF C36 0.1μF C39 0.1μF C41 0.1μF C40 0.
AD9786 R29 100Ω 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 3 4 5 6 7 8 9 10 2 AX13 3 AX12 4 AX11 5 AX10 6 AX09 7 AX08 8 AX07 1 AX06 2 AX05 3 AX04 4 AX03 5 AX02 6 AX01 7 AX00 8 1 2 3 4 5 6 7 8 9 10 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP6 DNP R1 R2 R3 R4 R5 R6 R7 R8 R9 AX00 R38 100
AD9786 R60 100Ω BX13 R64 100Ω 3 4 5 6 7 8 9 1 2 BX13 3 BX12 4 BX11 5 BX10 6 BX09 7 BX08 8 BX07 1 BX06 2 BX05 3 BX04 4 BX03 5 BX02 6 BX01 7 BX00 8 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 SDO 36 35 CLK 38 37 SDI 40 39 CSB 1 RIBBON J2 2 3 4 5 6 7 8 9 10 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP11 DNP R1
AD9786 DVDDS OPCLK_3 + C52 4.7μF 6.3V C53 0.1μF 10 PRE 11 9 J Q 13 CLK 12 7 K Q_ CLR 14 74LCX112 DGND;8 U7 DVDDS;16 2 SPCSB U5 1 12 4 U5 10 3 SPSDI U5 8 5 1 U6 2 13 74AC14 R21 10kΩ R20 10kΩ 3 R48 9kΩ U5 9 R45 9kΩ U6 11 4 U6 6 12 U6 DVDDS 10 74AC14 9 74AC14 U6 74AC14 74AC14 5 11 74AC14 74AC14 SPSDO U5 74AC14 74AC14 6 13 SPI PORT P1 1 2 3 4 5 6 74AC14 74AC14 SPCLK U5 R50 9kΩ U6 8 + C43 4.7μF 6.3V C50 0.1μF 74AC14 Figure 91.
03152-092 AD9786 03152-093 Figure 92. PCB Assembly, Primary Side, Rev. F Evaluation Board Figure 93. PCB Assembly, Secondary Side, Rev. F Evaluation Board Rev.
03152-094 AD9786 03152-095 Figure 94. PCB Assembly, Layer 1 Metal, Rev. F Evaluation Board Figure 95. PCB Assembly, Layer 6 Metal, Rev. F Evaluation Board Rev.
03152-096 AD9786 03152-097 Figure 96. PCB Assembly, Layer 2 Metal (Ground Plane),Rev. F Evaluation Board Figure 97. PCB Assembly, Layer 3 Metal (Power Plane),Rev. F Evaluation Board Rev.
03152-098 AD9786 03152-099 Figure 98. PCB Assembly, Layer 4 Metal (Power Plane), Rev. F Evaluation Board Figure 99. PCB Assembly, Layer 5 Metal (Ground Plane), Rev. F Evaluation Board Rev.
AD9786 OUTLINE DIMENSIONS 14.20 14.00 SQ 13.80 0.75 0.60 0.45 1.20 MAX 12.20 12.00 SQ 11.80 80 61 61 1 60 80 1 60 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) BOTTOM VIEW 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 6.00 BSC SQ 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY (PINS UP) 20 41 40 21 VIEW A 41 20 21 40 0.50 BSC LEAD PITCH 0.27 0.22 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 100.
AD9786 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03152-0-10/05(B) Rev.
