Datasheet

AD9785/AD9787/AD9788
Rev. A | Page 43 of 64
07098-104
NCO PHASE
ACCUMULATOR
RESET
RESET
GENERATOR
NCO
Δ
t
SYNC_I
ENABLE
SYNC_I
DELAY [4:0]
EDGE
DETECTOR
CODE
DEMODULATOR
SYNC ERROR
DETECTOR
CLOCK
GENERATION
STATE L D- STATE
CLOCK
STATE [3:0]
PULSE MODE
ENABLE
PN CODE MODE ENABLE
CORRELATE
THRESHOLD [4:0]
01
SYNC MODE
SELECT
SYNC TIMING
ERROR IRQ
DACCL
K
SYNC_I
(PIN 13, PIN 14)
TXENABLE
(PIN 39)
TRANSMIT
PATH
•
•
•
INTERNAL
CLOCKS
Figure 60. Synchronization Receive Circuitry Block Diagram
07098-102
SYSTEM CLOCK
PULSE
GENERATOR
LOW SKEW
CLOCK DRIVER
LOW SKEW
CLOCK DRIVER
M
A
TCHED
LENGTH TRACES
MATCHED
LENGTH TRACES
REFCLK
TXENABLE
SYNC_I
REFCLK
TXENABLE
SYNC_I
OUT
OUT
Figure 61. Multichip Synchronization in Pulse Mode