Datasheet

AD9785/AD9787/AD9788
Rev. A | Page 32 of 64
The frequency tuning word (FTW) register comprises four bytes located at Address 0x0A.
Table 20. Frequency Tuning Word (FTW) Register
Address Bit Name Description
0x0A [31:0]
Frequency Tuning
Word [31:0]
These bits make up the frequency tuning word applied to the NCO phase accumulator.
See the Numerically Controlled Oscillator section for details.
The phase control register (PCR) comprises four bytes located at Address 0x0B.
Table 21. Phase Control Register (PCR)
Address Bit Name Description
0x0B [31:26] Reserved Reserved for future use.
[25:16]
Phase Correction
Word [9:0]
These bits are the 10-bit phase correction word.
[15:0]
NCO Phase Offset
Word [15:0]
These bits are the 16-bit NCO phase offset word. See the Numerically Controlled Oscillator
section for details.
The amplitude scale factor (ASF) register comprises three bytes located at Address 0x0C.
Table 22. Amplitude Scale Factor (ASF) Register
Address Bit Name Description
0x0C [23:18] Reserved Reserved for future use.
[17:9]
Q DAC Amplitude
Scale Factor [8:0]
These bits are the 9-bit Q DAC amplitude scale factor. The bit weighting is MSB = 2
1
,
LSB = 2
−7
, which yields a multiplier range of 0 to 3.9921875. Note that by setting the gain to
1.0 (0x080), the gain block is bypassed. This changes the latency of the signal. Therefore, in
systems using quadrature signals, either both I and Q scale factors should be bypassed or
both should have gains set to a value other than 1.0.
[8:0]
I DAC Amplitude
Scale Factor [8:0]
These bits are the 9-bit I DAC amplitude scale factor. The bit weighting is MSB = 2
1
,
LSB = 2
−7
, which yields a multiplier range of 0 to 3.9921875.
The output offset (OOF) register comprises four bytes located at Address 0x0D.
Table 23. Output Offset (OOF) Register
Address Bit Name Description
0x0D [31:16] Q DAC Offset [15:0] These bits are the 16-bit Q DAC offset factor. The LSB bit weight is 2
0
.
[15:0] I DAC Offset [15:0] These bits are the 16-bit I DAC offset factor. The LSB bit weight is 2
0
.
The version register (VR) comprises two bytes located at Address 0x0E and is read only.
Table 24. Version Register (VR)
Address Bit Name Description
0x0E [15:8] Reserved Reserved for future use.
[7:0] Version ID These bits read back the current version of the product.