Datasheet
AD9785/AD9787/AD9788
Rev. A | Page 21 of 64
THEORY OF OPERATION
The AD9785/AD9787/AD9788 devices combine many features
that make them very attractive DACs for wired and wireless
communications systems. The dual digital signal path and dual
DAC structure allow an easy interface to common quadrature
modulators when designing single sideband transmitters. The
speed and performance of the AD9785/AD9787/AD9788 allow
wider bandwidths and more carriers to be synthesized than in
previously available DACs. In addition, these devices include
an innovative low power, 32-bit complex NCO that greatly
increases the ease of frequency placement.
The AD9785/AD9787/AD9788 offer features that allow
simplified synchronization with incoming data and between
multiple parts, as well as the capability to phase synchronize
NCOs on multiple devices. Auxiliary DACs are also provided
on chip for output dc offset compensation (for LO compen-
sation in SSB transmitters) and for gain matching (for image
rejection optimization in SSB transmitters). Another innovative
feature in the devices is the digitally programmable output
phase compensation, which increases the amount of image
cancellation capability in SSB (single sideband) transmitters.
SERIAL PORT INTERFACE
The AD9785/AD9787/AD9788 serial port is a flexible,
synchronous serial communications port allowing easy
interface to many industry-standard microcontrollers and
microprocessors. The serial I/O is compatible with most
synchronous transfer formats, including both the Motorola®
6905/11 SPI and the Intel® 8051 SSR protocols.
The serial interface allows read/write access to all registers that
configure the AD9785/AD9787/AD9788. MSB first and LSB
first transfer formats are supported. In addition, the serial
interface port can be configured as a single-pin I/O (SDIO),
which allows a 3-wire interface, or two unidirectional pins for
input/output (SDIO/SDO), which enables a 4-wire interface.
One optional pin, SPI_CSB (chip select), allows enabling of
multiple devices on a single bus.
With the AD9785/AD9787/AD9788, the instruction byte
specifies read/write operation and the register address. Serial
operations on the AD9785/AD9787/AD9788 occur only at the
register level, not at the byte level, due to the lack of byte
address space in the instruction byte.
07098-002
INTERNAL CLOCK TIMING AND CONTROL LOGIC
DELAY
LINE
DELAY
LINE
DELAY
LINE
SYNC_O
DATACLK
SYNC_I
P1D[15:0]
TXENABLE
P2D[15:0]
16-BIT
DAC1
OUT1_P
OUT1_N
16-BIT
DAC2
OUT2_P
OUT2_N
AUX1_N
VREF
AUX1_P
AUX2_N
AUX2_P
RESET
REFCLK+
REFCLK–
REFERENCE
AND BIAS
AUX1
AUX2
CLK
R
CVR
CLOCK
MULTIPLIER
(2× – 16×)
POWER-ON
RESET
PLL CONTROL
DAC_CLK
0
1
PLL_LOCK
RESET
IRQ
10
10
10
10
GAIN1
GAIN2
HB1_CLK
HB2_CLK
HB3_CLK
INTERPOLATION
FACTOR
SERIAL
I/O
PORT
PROGRAMMING
REGISTERS
SPI_SDO
SPI_SDIO
SCLK
SPI_CSB
MULTICHIP
SYNCHRONIZATION
1
0
LVDS
LVDS
DATA ASSEMBLER
QUAD
HB
FILTER
(2×)
QUAD
HB
FILTER
(2×)
QUAD
HB
FILTER
(2×)
16
16
1
2
3
0
2
1
0
3
+
+
+
+
NCO
ω
θ
16
16
16
10
16
16
32
COS
Q-SCALE
SIN
FREQUENCY
PHASE
PHASE
CORRECTION
INV_SINC_EN
×
SIN(×)
0
1
×
SIN(×)
0
1
I-SCALE
Q-OFFSET
I-OFFSET
Figure 42. Functional Block Diagram