Dual 12-/14-/16-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO AD9785/AD9787/AD9788 FEATURES GENERAL DESCRIPTION Analog output: adjustable 8.7 mA to 31.
AD9785/AD9787/AD9788 TABLE OF CONTENTS Features .............................................................................................. 1 Input Data RAM ......................................................................... 37 Applications ....................................................................................... 1 Digital Datapath ............................................................................. 38 General Description ..................................................
AD9785/AD9787/AD9788 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE 1596 reduced range link, unless otherwise noted. Table 1.
AD9785/AD9787/AD9788 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2.
AD9785/AD9787/AD9788 Parameter LATENCY (DACCLK CYCLES) 1× Interpolation 2× Interpolation 4× Interpolation 8× Interpolation Inverse Sinc POWER-UP TIME2 DAC Wake-Up Time3 DAC Sleep Time4 Test Conditions/Comments Min With or without modulation With or without modulation With or without modulation With or without modulation Typ Max 40 83 155 294 18 260 22 22 IOUT current settling to 1% IOUT current to less than 1% of full scale Unit Cycles Cycles Cycles Cycles Cycles ms ms ms 1 Timing vs.
AD9785/AD9787/AD9788 ABSOLUTE MAXIMUM RATINGS Table 4.
AD9785/AD9787/AD9788 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 I120 74 VREF 73 IPTAT 4 72 AGND REFCLK+ 5 71 IRQ REFCLK– 6 70 RESET CGND 7 69 SPI_CSB CGND 8 68 SCLK CVDD18 9 67 SPI_SDIO 66 SPI_SDO 65 PLL_LOCK AGND 12 6
AD9785/AD9787/AD9788 Pin No.
AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 AD9785/AD9787/AD9788 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 I120 74 VREF 73 IPTAT 4 72 AGND REFCLK+ 5 71 IRQ REFCLK– 6 70 RESET CGND 7 69 SPI_CSB CGND 8 68 SCLK CVDD18 9 AD9787 67 SPI_SDIO TOP VIEW (Not to Scale) 66 SPI_SDO 65 PLL_LOCK AGND 12 64 DGND SY
AD9785/AD9787/AD9788 Pin No.
AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 AD9785/AD9787/AD9788 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 CVDD18 2 75 I120 74 CGND 3 VREF 73 CGND IPTAT 4 72 AGND REFCLK+ 5 71 IRQ REFCLK– 6 70 RESET CGND 7 69 SPI_CSB CGND 8 68 SCLK CVDD18 9 AD9788 67 SPI_SDIO TOP VIEW (Not to Scale) 66 SPI_SDO
AD9785/AD9787/AD9788 Pin No.
AD9785/AD9787/AD9788 TYPICAL PERFORMANCE CHARACTERISTICS –142 100 95 –146 250 MSPS 85 2× SFDR (dB) NSD (dBm/Hz) –150 –154 1× –158 200 MSPS 90 4× 160 MSPS 80 75 70 65 –162 60 –166 0 20 40 60 80 100 fOUT (MHz) 50 0 20 40 60 100 80 fOUT (MHz) Figure 5. AD9785 Noise Spectral Density vs. fOUT, Multitone Input, fDATA = 200 MSPS 07098-067 55 07098-064 –170 Figure 8. AD9785 In-Band SFDR vs.
–142 –60 –146 –65 –150 NSD (dBm/Hz) –55 –70 FIRST ADJ CHAN –75 SECOND ADJ CHAN –85 –90 20 40 60 –158 1× 2× 4× –162 –166 THIRD ADJ CHAN 0 –154 80 100 120 140 160 180 200 220 240 260 fOUT (MHz) –170 0 20 40 60 80 100 07098-073 –80 07098-070 ACLR (dBc) AD9785/AD9787/AD9788 fOUT (MHz) Figure 14. AD9787 Noise Spectral Density vs. fOUT over Output Frequency of Multitone Input, fDATA = 200 MSPS Figure 11. AD9787 ACLR, 4× Interpolation, fDATA = 122.
AD9785/AD9787/AD9788 –55 100 –60 200MSPS 90 0 dBFS PLL ON –70 IMD (dBc) ACLR (dBc) –65 –6 dBFS PLL OFF –75 80 160MSPS 250MSPS 70 –80 60 –85 –3 dBFS PLL OFF 20 40 60 80 100 120 140 160 180 200 220 240 260 fOUT (MHz) 50 0 50 100 150 200 07098-080 0 0 dBFS PLL OFF 07098-077 –90 fOUT (MHz) Figure 17. AD9788 ACLR for Second Adjacent Band WCDMA, 4× Interpolation, fDATA = 122.88 MSPS, NCO Translates Baseband Signal to IF Figure 20. AD9788 IMD vs.
AD9785/AD9787/AD9788 100 100 95 90 90 80 80 IMD (dBc) IMD (dBc) 85 75MSPS 70 50MSPS 75 70 100MSPS 65 60 60 55 50 100 150 200 250 300 350 400 450 fOUT (MHz) 50 0 40 80 120 160 200 240 280 320 360 400 07098-086 0 07098-083 50 fOUT (MHz) Figure 23. AD9788 IMD vs. fOUT, 8× Interpolation Figure 26. AD9788 IMD vs.
AD9785/AD9787/AD9788 –142 90 –146 85 160MSPS 75 SFDR (dB) –154 –158 2× 250MSPS 65 4× –162 60 8× –166 55 0 10 20 30 40 50 07098-089 –170 70 50 fOUT (MHz) 0 20 40 60 80 100 fOUT (MHz) Figure 29. AD9788 Noise Spectral Density vs. fOUT, Single-Tone Input, fDATA = 100 MSPS 07098-092 NSD (dBm/Hz) –150 Figure 32. AD9788 In-Band SFDR vs.
AD9785/AD9787/AD9788 110 100 100MSPS 95 100 150MSPS 250MSPS 85 90 200MSPS SFDR (dB) SFDR (dB) 160MSPS 90 80 70 200MSPS 80 75 70 65 60 60 10 20 30 40 50 60 70 80 90 fOUT (MHz) 50 07098-095 0 100MSPS 80 100 50MSPS 150MSPS 90 80 60 70 55 60 20 30 40 50 60 70 80 90 fOUT (MHz) 50 07098-096 10 20 30 40 50 45 Figure 39. AD9788 In-Band SFDR vs. fOUT, 8× Interpolation 90 –3dBFS 0dBFS 10 fOUT (MHz) Figure 36. AD9788 Out-of-Band SFDR vs.
AD9785/AD9787/AD9788 110 PLL OFF 100 PLL ON SFDR (dB) 90 80 70 50 0 10 20 30 fOUT (MHz) 40 50 07098-101 60 Figure 41. AD9788 In-Band SFDR vs. fOUT, 4× Interpolation, fDATA = 100 MSPS, PLL On/PLL Off Rev.
AD9785/AD9787/AD9788 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases.
AD9785/AD9787/AD9788 THEORY OF OPERATION The AD9785/AD9787/AD9788 devices combine many features that make them very attractive DACs for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband transmitters. The speed and performance of the AD9785/AD9787/AD9788 allow wider bandwidths and more carriers to be synthesized than in previously available DACs.
AD9785/AD9787/AD9788 For example, when accessing the frequency tuning word (FTW) register, which is four bytes wide, Phase 2 requires that four bytes be transferred. If accessing the amplitude scale factor (ASF) register, which is three bytes wide, Phase 2 requires that three bytes be transferred. After transferring all data bytes per the instruction byte, the communication cycle is completed.
AD9785/AD9787/AD9788 Instruction Byte SPI_SDO—Serial Data Output The instruction byte contains the following information as shown in the instruction byte bit map. Instruction Byte Information Bit Map MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 R/W X X A4 A3 A2 A1 A0 R/W—Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation.
AD9785/AD9787/AD9788 SPI REGISTER MAP When reading Table 9, note that the AD9785/AD9787/AD9788 is a 32-bit part and, therefore, the 4th through the 11th columns (beginning with the MSB and ending with the LSB) represent a set of eight bits. Refer to the Bit Range column for the actual bits being described. Table 9. Address 0x00 0x01 Register Name Comm.
AD9785/AD9787/AD9788 Address 0x0B Register Name Phase Control Register Bit Range [15:0] [23:16] MSB MSB − 1 [31:24] 0x0C Amplitude Scale Factor Register Reserved [7:0] [15:8] 0x0E1 0x1D1 0x1E 1 Output Offset Register Version Register RAM Test Register MSB − 5 MSB − 6 LSB Phase Correction Word [9:8] I DAC Amplitude Scale Factor [7:0] Q DAC Amplitude Scale Factor [6:0] [23:16] 0x0D MSB − 2 MSB − 3 MSB − 4 NCO Phase Offset Word [15:0] Phase Correction Word [7:0] Reserved [15:0] [31:16] I D
AD9785/AD9787/AD9788 The digital control (DCTL) register comprises two bytes located at Address 0x01. Table 11.
AD9785/AD9787/AD9788 The data synchronization control register (DSCR) comprises two bytes located at Address 0x02. Table 12. Data Synchronization Control Register (DSCR) Address 0x02 Bit [15:11] Name DATACLK Delay [4:0] [10:7] Data Timing Margin [3:0] [6] LVDS data clock enable [5] DATACLK invert [4] DATACLK delay enable [3] Data timing mode [2] [1] Set high Data sync polarity [0] Reserved Description Controls the amount of delay applied to the output data clock signal.
AD9785/AD9787/AD9788 The multichip synchronization register (MSCR) comprises four bytes located at Address 0x03. Table 13.
AD9785/AD9787/AD9788 The PLL control (PLLCTL) register comprises three bytes located at Address 0x04. These bits are routed directly to the periphery of the digital logic. No digital functionality within the main digital block is required. Table 14.
AD9785/AD9787/AD9788 The Auxiliary DAC 1 control register comprises two bytes located at Address 0x06. These bits are routed directly to the periphery of the digital logic. No digital functionality within the main digital block is required. Table 16. Auxiliary DAC 1 Control Register Address 0x06 Bit [15] Name Auxiliary DAC 1 sign [14] Auxiliary DAC 1 current direction [13] Auxiliary DAC 1 power-down [12:10] [9:0] Reserved Auxiliary DAC 1 data Description 0: Default.
AD9785/AD9787/AD9788 The interrupt control register comprises two bytes located at Address 0x09. Bits [11:10] and Bits [7:3] are read-only bits that indicate the current status of a specific event that may cause an interrupt request (IRQ pin active low). These bits are controlled via the digital logic and are read only via the serial port. Bits [1:0] are the IRQ mask (or enable) bits, which are writable by the user and can also be read back. Table 19.
AD9785/AD9787/AD9788 The frequency tuning word (FTW) register comprises four bytes located at Address 0x0A. Table 20. Frequency Tuning Word (FTW) Register Address 0x0A Bit [31:0] Name Frequency Tuning Word [31:0] Description These bits make up the frequency tuning word applied to the NCO phase accumulator. See the Numerically Controlled Oscillator section for details. The phase control register (PCR) comprises four bytes located at Address 0x0B. Table 21.
AD9785/AD9787/AD9788 INPUT DATA PORTS The AD9785/AD9787/AD9788 can operate in two data input modes: dual-port mode and single-port mode. In the default dual-port mode (single-port mode = 0), each DAC receives data from a dedicated input port. In single-port mode (single-port mode = 1), both DACs receive data from Port 1. In single-port mode, DAC 1 and DAC 2 data is interleaved and the TXENABLE input is used to steer data to the intended DAC.
AD9785/AD9787/AD9788 DATACLK tSDATACLK 07098-112 tHDATACLK INPUT DATA Figure 47. DATACLK Timing DATACLK P1D[15:0] P1D(1) P1D(2) P1D(3) P1D(4) P1D(5) P1D(6) P1D(7) P1D(8) TXENABLE SMP_CLK P1D_SMP[15:0] P1D(1) P1D(2) P1D(3) P1D(4) P1D(5) P1D(6) P1D(7) P1D(8) QFIRST = 0 QFIRST = 1 I DAC[15:0] P1D(1) P1D(3) P1D(5) Q DAC[15:0] P1D(2) P1D(4) P1D(6) I DAC[15:0] P1D(1) P1D(3) P1D(5) P1D(4) P1D(6) Q DAC[15:0] 07098-110 IQSEL_SMP Figure 48.
AD9785/AD9787/AD9788 Setting the Frequency of DATACLK INPUT DATA REFERENCED TO REFCLK The DATACLK signal is derived from the internal DAC sample clock, DACCLK. The frequency of DATACLK output depends on several programmable settings. The relationship between the frequency of DACCLK and DATACLK is In some systems, it may be more convenient to use the REFCLK input instead of the DATACLK output as the input data timing reference.
AD9785/AD9787/AD9788 SYNC_I tH_SYNC tS_SYNC DACCLK REFCLK tSREFCLK 07098-111 tHREFCLK INPUT DATA Figure 51. REFCLK 8× OPTIMIZING THE DATA INPUT TIMING The AD9785/AD9787/AD9788 have on-chip circuitry that enables the user to optimize the input data timing by adjusting the relationship between the DATACLK output and DCLK_SMP, the internal clock that samples the input data. This optimization is made by a sequence of SPI register read and write operations.
AD9785/AD9787/AD9788 Manual Timing Optimization Mode When the device is operating in manual timing optimization mode (Register 0x02, Bit 3 = 0), the device does not alter the DATACLK Delay [4:0] value that is programmed by the user. By default, the DATACLK delay enable is inactive. This bit must be set high for the DATACLK Delay [4:0] value to be realized. The delay (in absolute time) when programming the DATACLK delay from 00000 to 11111 varies from about 700 ps to about 6.5 ns.
AD9785/AD9787/AD9788 DIGITAL DATAPATH 10 The AD9785/AD9787/AD9788 digital datapath consists of three 2× half-band interpolation filters, a quadrature modulator, and an inverse sinc filter. A 32-bit NCO provides the sine and cosine carrier signals required for the quadrature modulator. 0 –10 ATTENUATION (dB) –20 INTERPOLATION FILTERS The AD9785/AD9787/AD9788 contain three half-band filters that can be bypassed.
AD9785/AD9787/AD9788 Table 29. Half-Band Filter 2 Table 28.
AD9785/AD9787/AD9788 results in an output signal that is offset by a constant angle relative to the nominal signal. This allows the user to phase align the NCO output with some external signal, if necessary. This can be especially useful when NCOs of multiple AD9785/ AD9787/AD9788 devices are programmed for synchronization. The phase offset allows for the adjustment of the output timing between the devices.
AD9785/AD9787/AD9788 Upper Coefficient H(9) H(8) H(7) H(6) – Integer Value +2 −4 +10 −35 +401 IOUTx_P (mA) Lower Coefficient H(1) H(2) H(3) H(4) H(5) The inverse sinc filter is disabled by default. It can be enabled by setting the inverse sinc enable bit (Bit 9) in Register 0x01. 20 0 15 5 10 10 5 15 IOUTx_N (mA) Table 31.
AD9785/AD9787/AD9788 DEVICE SYNCHRONIZATION System demands may impose two different requirements for synchronization. Some systems require multiple DACs to be synchronized to each other, for example, a system that supports transmit diversity or beamforming, where multiple antennas are used to transmit a correlated signal. In this case, the DAC outputs need to be phase aligned with each other, but there may not be a requirement for the DAC outputs to be aligned with a systemlevel reference clock.
AD9785/AD9787/AD9788 DACCLK CLOCK GENERATION NCO PHASE ACCUMULATOR STATE RESET • • • INTERNAL CLOCKS LD-STATE CLOCK STATE [3:0] NCO RESET GENERATOR TXENABLE (PIN 39) TRANSMIT PATH PULSE MODE ENABLE 0 1 SYNC MODE SELECT EDGE DETECTOR Δt CODE DEMODULATOR SYNC_I DELAY [4:0] SYNC_I ENABLE PN CODE MODE ENABLE CORRELATE THRESHOLD [4:0] SYNC ERROR DETECTOR SYNC TIMING ERROR IRQ 07098-104 SYNC_I (PIN 13, PIN 14) Figure 60.
AD9785/AD9787/AD9788 high logic level pin, the strobe signal should be a low logic level pulse unless the TXENABLE invert bit is set in the SPI. SYNCHRONIZING DEVICES TO A SYSTEM CLOCK The AD9785/AD9787/AD9788 offer a pulse mode synchronization scheme (see Figure 61) to align the DAC outputs of multiple devices within a system to the same DAC clock edge. The pulse mode synchronization scheme is a two-part operation.
AD9785/AD9787/AD9788 6. Table 32 shows the register settings required to enable the pulse mode synchronization feature. Table 32. Register Settings for Enabling Pulse Sync Mode Register 0x01 0x03 Bit [13] [12] [11] [26] [25] [10] Parameter PN code sync enable Sync mode select Pulse sync enable SYNC_I enable SYNC_O enable Set high Value 0 0 1 1 0 1 7.
AD9785/AD9787/AD9788 The Correlate Threshold [4:0] value (Register 0x03, Bits [31:27]) indicates how closely the code of the received SYNC_I signal is to the expected code. A high threshold requires a closer match of the encoded signal to set the sync lock status bit; a lower value reduces the matching requirements to set the sync lock status bit. Table 33 lists the register settings required to enable the PN code mode synchronization feature. Table 33.
AD9785/AD9787/AD9788 DRIVING THE REFCLK INPUT The REFCLK input requires a low jitter differential drive signal. REFCLK is a PMOS input differential pair powered from the 1.8 V supply; therefore, it is important to maintain the specified 400 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 1 V p-p about the 400 mV common-mode voltage. Although these input levels are not directly LVDScompatible, REFCLK can be driven by an offset ac-coupled LVDS signal, as shown in Figure 65. 0.
AD9785/AD9787/AD9788 REFCLK (PIN 5 AND PIN 6) PHASE DETECTION 0x04 [23:21] VCO CONTROL VOLTAGE ADC PLL_LOCK (PIN 65) 0x09 [3] LOOP FILTER VCO ÷N2 ÷N1 0x04 [12:11] PLL LOOP DIVISOR 0x04 [14:13] PLL VCO DIVISOR ÷IF DAC INTERPOLATION RATE DATACLK (PIN 37) 0x04 [15] PLL ENABLE DAC CLOCK 07098-027 0x01 [7:6] Figure 68. Clock Multiplication Circuit Table 35. Typical VCO Freq Range vs.
AD9785/AD9787/AD9788 4. Configuring the PLL Band Select Value The PLL VCO has a valid operating range from approximately 1.0 GHz to 2.0 GHz covered in 63 overlapping frequency bands as shown in Table 35. For any desired VCO output frequency, there are multiple valid PLL band select values. Note that the data shown in Table 35 is for a typical device. Device-to-device variations can shift the actual VCO output frequency range by 30 MHz to 40 MHz.
AD9785/AD9787/AD9788 ANALOG OUTPUTS Full-scale current on the I DAC and Q DAC can be set from 8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is used to set up a current in an external resistor connected to I120 (Pin 75). A simplified block diagram of the reference circuitry is shown in Figure 69. AD9788 I DAC GAIN 1.2V BAND GAP REFERENCE 5kΩ I DAC CURRENT SCALING I120 0.1µF Gain scaling of the analog DAC output can be achieved by changing the values in Register 0x05 and Register 0x07.
AD9785/AD9787/AD9788 There are two output signals on each auxiliary DAC. One signal is designated P, the other N. The sign bit in each auxiliary DAC control register (Bit 15) controls whether the P side or the N side of the auxiliary DAC is turned on. Only one side of the auxiliary DAC is active at a time. The auxiliary DAC structure is shown in Figure 71. 0 TO 2mA (SOURCE) The choice of sinking or sourcing should be made at circuit design time.
AD9785/AD9787/AD9788 POWER DISSIPATION Figure 74 through Figure 78 detail the power dissipation of the AD9785/AD9787/AD9788 under a variety of operating conditions. All of the graphs are taken with data being supplied to both the I and Q channels. The power consumption of the device does not vary significantly with changes in the modulation mode or analog output frequency. Graphs of the total power dissipation are shown along with the power dissipation of the DVDD18, DVDD33, and CVDD18 supplies.
AD9785/AD9787/AD9788 140 120 POWER (mW) 100 80 60 40 0 0 200 400 600 fDAC (MSPS) 800 1000 07098-039 20 Figure 78. Digital 1.8 V Supply, Power Dissipation of Inverse Sinc Filter Rev.
AD9785/AD9787/AD9788 AD9785/AD9787/AD9788 EVALUATION BOARDS The factory default jumper configuration is as follows: The remainder of this data sheet describes the evaluation boards for testing the AD9785, AD9787, and AD9788 devices. Jumpers JP2, JP3, JP4, and JP8 are unsoldered. OUTPUT CONFIGURATION Jumpers JP14, JP15, JP16, and JP17 are soldered. Each evaluation board contains an Analog Devices ADL5372 quadrature modulator.
AD9785/AD9787/AD9788 EVALUATION BOARD SOFTWARE A GUI .exe file for Microsoft® Windows® is included on the CD that ships with the evaluation board. This file allows the user to easily program all the functions on the AD9785/AD9787/AD9788. Figure 80 shows this user interface. The most important features for configuring the AD9785/AD9787/AD9788 are called out in the figure.
Rev. A | Page 56 of 64 C20 C76 C77 Figure 81. Evaluation Board, Power Supply and Decoupling 16V 22UF DVDD33_IN C21 TP6 RED 22UF 16V AVDD33_IN TP5 RED 16V 22UF DVDD18_IN 16V 22UF CVDD18_IN ACASE ACASE ACASE RED TP3 ACASE TP20 RED RED TP19 RED TP18 RED TP17 .1UF C45 CC0603 .1UF LC1812 L4 EXC-CL4532U1 C28 CC0603 .1UF LC1812 L3 EXC-CL4532U1 C71 CC0603 .1UF LC1812 L2 EXC-CL4532U1 C68 CC0603 LC1812 L1 .1UF C42 CC0603 .1UF C26 CC0603 .
AD9785/AD9787/AD9788 IOUT_N IOUT-IOUT_P AUX1_P AUX1_N AUX2_P AUX2_N S8 2 R 12 RC 060 3 R3 RC 060 3 RC 060 3 RC 060 3 RC0603 50 0 RC0603 50 0 RC0603 50 0 RC0603 50 0 1 R 15 R 17 S5 2 250 1 R2 250 R4 250 R14 250 R16 R 20 RC 060 3 R 19 0 RC 060 3 DNP JP1 JP5 JP6 JP11 6 4 1 3 T2B ADTL1-12 P TC1-1T T2A IP IN QP QN S 4 6 3 1 1 2 3 6 4 T1B ADTL1-12 P TC1-1T T1A C62 C61 .
D2P D2N D1N VAL C65 CC0603 VAL C7 4 CC0603 VAL C80 CC0603 VAL L9 VAL LC0805 VAL LC0805 L8 L11 VAL LC0805 VAL C64 CC0603 VAL C7 5 CC0603 VAL C79 CC0603 GND 10UF 10V C43 VDDM GND ACASE JP12 R24 100PF CC0402 RC0603 R23 DNP C50 RC0603 RC0603 C82 DNP CC0402 .1UF C47 10K R25 MOD_QP MOD_QN VDDM MOD_IN J4 6 5 4 3 2 1 MOD_QP MOD_QN Figure 83.
J1 2 1 R13 VAL 5 P 1 2 ETC1-1-13 S 3 .1UF CC040 2 C23 .1UF CC040 2 4 T2 25 R29 25 R28 RC040 2 RC040 2 RC040 2 RC040 2 C19 300 R31 R30 1K CC0402 CC0402 .1UF C17 DNP C16 CVDD18 CLK_N CLK_P AD9785/AD9787/AD9788 Figure 84. Evaluation Board, TxDAC Clock Interface Rev.
Rev. A | Page 60 of 64 B17 B18 B19 B20 B21 B22 B23 B24 B25 A17 A18 A19 A20 A21 A22 A23 A24 A25 PKG_TYPE=MOLEX110 VAL B16 A16 PKG_TYPE=MOLEX110 VAL B15 A15 B11 B8 A8 A11 C9 B7 A7 B9 B6 A6 B10 B5 A5 A9 B4 A4 A10 C8 B3 A3 Figure 85.
Figure 86. Evaluation Board, On-Board Power Supply Rev.
AD9785/AD9787/AD9788 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 1 SEATING PLANE 76 76 75 100 1 75 PIN 1 BOTTOM VIEW (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 25 26 0.20 0.09 51 50 25 50 1.05 1.00 0.95 7° 3.5° 0° 0.50 BSC 0.27 0.22 0.17 0.15 0.05 26 6.50 NOM COPLANARITY 0.08 121207-A COMPLIANT TO JEDEC STANDARDS MS-026-AED-HDT NOTES: 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2.
AD9785/AD9787/AD9788 NOTES Rev.
AD9785/AD9787/AD9788 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07098-0-2/09(A) Rev.
