Datasheet

Quick Start Guide

AD9783/81/80-DPG2-EBZ

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D00000-0-1/07(A)

Selecting the Modulator Outputs

By default, solder jumpers JP4, JP5, JP6, and JP7 configure the evaluation board for the DAC outputs to be observed at SMA J5 for

IOUT1P and J9 for IOUT2P. This jumper setting is shown in 8 a). To connect to the filter that feed ADL5375 the solder jumpers

need to be repositioned as shown in 8 b). The output from the ADL5375 Modulator can be observed SMA J6, RF out.

Figure 8 – a) DAC Output Configuration b) Modulator Output Configuration

AD9783 SPI Application

The SPI application is split into two sections. On the left are the controls for DAC and the right side are the SPI registers as read

back from the part. The left side of the panel allows control of the different features of the AD9783 but can be left in the default

positions if you are not running at the very high sample rate>350MSPS . The functions provided by the SPI application are

described here, as they relate to the evaluation board. For complete descriptions of each register, refer to the AD9783/1/0

datasheet. In the interest of continuous quality improvements, the images below may not exactly match your version of the

software. In order to set the registers with the VI you must click the mouse on the arrow under the edit for updating what is

selected below or the right circular arrows continuously updates as features are selected in the various sections of the VI

Power Down Control

The first set of switched on the far left let you power down the DACs, or Aux DACs, Data,

Data format

The part defaults to two’s compliments but can be changed to unsigned binary.

Seek

The Seek bit is used for optimizing the setup, hold and timing delays for high sample rates as described in the data sheet.

DAC Mode

The main DACs can be used in normal mode, mix mode or return to Zero mode. The registers below also allow

DATA Clock

The data clock section includes control for Data clk delay if needed for adjusting the timing on the interface.

PLL Control

The AD9779A has an on-chip PLL. When

PLL_ENABLE

is turned on, the chip will automatically select the appropriate band using

the Divder1 and Divider0 values. The VCO Frequency must be between 1 and 2 GHz for proper operation. The auto-band select

can be bypassed by enabling

PLL MANUAL

and entering a band in PLL Band Select. Divider1 and Divider0 must still be chosen

appropriately in this mode of operation.

Main DAC Control

This section controls the two main DACs in the AD9783. The Full-Scale Current of each DAC can be set with the

I DAC Gain

and

DAC Gain

controls. The 512 default is for 20ma outputs.

Aux DAC Control

The Aux DAC control section is used to program aux DACs for LO and image suppression out the output of the AQM. The default is