Datasheet

AD9780/AD9781/AD9783 Data Sheet
Rev. B | Page 4 of 32
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
OUTFS
= 20 mA maximum sample rate, unless
otherwise noted.
Table 2.
Parameter Min Typ Max Unit
DAC CLOCK INPUT (CLKP, CLKN)
Differential Peak-to-Peak Voltage (CLKP − CLKN) 400 800 1600 mV
Common-Mode Voltage 300 400 500 mV
Maximum Clock Rate 500 MSPS
DAC CLOCK TO ANALOG OUTPUT DATA LATENCY 7 Cycles
SERIAL PERIPHERAL INTERFACE (CMOS INTERFACE)
Maximum Clock Rate (SCLK) 40 MHz
Minimum Pulse Width High 12.5 ns
Minimum Pulse Width Low 12.5 ns
Setup time, SDI to SCLK (t
DS
) 2.0 ns
Hold Time , SDI to to SCLK (t
DH
) 0.2 ns
Data Valid ,SDO to SCLK, (t
DV
) 2.3 ns
Setup time, CSB to SCLK (t
DCSB
) 1.4 ns
SERIAL PERIPHERAL INTERFACE LOGIC LEVELS
Input Logic High 2.0 V
Input Logic Low 0.8 V
DIGITAL INPUT DATA (LVDS INTERFACE)
Input Voltage Range, V
IA
or V
IB
800 1600 mV
Input Differential Threshold, V
IDTH
−100 +100 mV
Input Differential Hysteresis, V
IDTHH
to V
IDTHL
20 mV
Input Differential Input Impedance, R
IN
80 120 Ω
Maximum LVDS Input Rate (per DAC)
500
MSPS