Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) LFCSP 72 VQ

Dual 12-/14-/16-Bit,

LVDS Interface, 500 MSPS DACs

Data Sheet

AD9780/AD9781/AD9783

Rev. B

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FEATURES

High dynamic range, dual DAC parts

Low noise and intermodulation distortion

Single carrier W-CDMA ACLR = 80 dBc @ 61.44 MHz IF

Innovative switching output stage permits usable outputs

beyond Nyquist frequency

LVDS inputs with dual-port or optional interleaved single-

port operation

Differential analog current outputs are programmable from

8.6 mA to 31.7 mA full scale

Auxiliary 10-bit current DACs with source/sink capability for

external offset nulling

Internal 1.2 V precision reference voltage source

Operates from 1.8 V and 3.3 V supplies

315 mW power dissipation

Small footprint, RoHS compliant, 72-lead LFCSP

APPLICATIONS

Wireless infrastructure

W-CDMA, CDMA2000, TD-SCDMA, WiMAX

Wideband communications

LMDS/MMDS, point-to-point

RF signal generators, arbitrary waveform generators

GENERAL DESCRIPTION

The AD9780/AD9781/AD9783 include pin-compatible, high

dynamic range, dual digital-to-analog converters (DACs) with

12-/14-/16-bit resolutions, and sample rates of up to 500 MSPS.

The devices include specific features for direct conversion transmit

applications, including gain and offset compensation, and they

interface seamlessly with analog quadrature modulators such as

the ADL5370.

A proprietary, dynamic output architecture permits synthesis

of analog outputs even above Nyquist by shifting energy away

from the fundamental and into the image frequency.

Full programmability is provided through a serial peripheral

interface (SPI) port. Some pin-programmable features are also

offered for those applications without a controller.

PRODUCT HIGHLIGHTS

1. Low noise and intermodulation distortion (IMD) enable

high quality synthesis of wideband signals.

2. Proprietary switching output for enhanced dynamic

performance.

3. Programmable current outputs and dual auxiliary DACs

provide flexibility and system enhancements.

FUNCTIONAL BLOCK DIAGRAM

GAIN

DAC

GAIN

DAC

OFFSET

DAC

OFFSET

DAC

16-BIT

I DAC

16-BIT

Q DAC

INTERFACE LOGIC

INTERNAL

REFERENCE

AND

BIAS

SERIAL

PERIPHERAL

INTERFACE

DEINTERLEAVING

LOGIC

CLKP

CLKN

LVDS

INTERFACE

D[15:0]

, V

SDO

SDIO

SCLK

CSB

REFIO

RESET

AUX2N

AUX2P

AUX1N

AUX1P

IOUT2N

IOUT2P

IOUT1N

IOUT1P

AD9783 DUAL LVDS DAC

06936-001

Figure 1.

Summary of content (32 pages)

PAGE 1
Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs AD9780/AD9781/AD9783 Data Sheet FEATURES GENERAL DESCRIPTION High dynamic range, dual DAC parts Low noise and intermodulation distortion Single carrier W-CDMA ACLR = 80 dBc @ 61.44 MHz IF Innovative switching output stage permits usable outputs beyond Nyquist frequency LVDS inputs with dual-port or optional interleaved singleport operation Differential analog current outputs are programmable from 8.6 mA to 31.
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AD9780/AD9781/AD9783 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 General Operation of the Serial Interface ............................... 19 Applications ....................................................................................... 1 Instruction Byte .......................................................................... 19 General Description .......................................................
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Data Sheet AD9780/AD9781/AD9783 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless otherwise noted. Table 1.
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AD9780/AD9781/AD9783 Data Sheet DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless otherwise noted. Table 2.
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Data Sheet AD9780/AD9781/AD9783 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 3.
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AD9780/AD9781/AD9783 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter AVDD33, DVDD33 DVDD18, CVDD18 AGND DGND CGND REFIO With Respect to AGND, DGND, CGND AGND, DGND, CGND DGND, CGND AGND, CGND AGND, DGND AGND IOUT1P, IOUT1N, IOUT2P, IOUT2N, AUX1P, AUX1N, AUX2P, AUX2N D15 to D0 AGND CLKP, CLKN CGND CSB, SCLK, SDIO, SDO DGND Junction Temperature Storage Temperature DGND Rating −0.3 V to +3.6 V −0.3 V to +1.98 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.
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Data Sheet AD9780/AD9781/AD9783 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9780 (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FS ADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC NC NC NC NC NC NC D0N D0P D6P D6N D5P D5N D4P D4N DCOP DCON DVDD33 DVSS DCIP D
PAGE 8
Data Sheet 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO AD9780/AD9781/AD9783 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9781 (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FS ADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC NC NC D0N D0P D1N D1P D2N D2P D8P D8N D7P D7N D6P D6N DCOP DCON DVDD33 DVSS DCIP DCIN D5P D5N D4P D4N D3P D3N 19 20 21 22 2
PAGE 9
AD9780/AD9781/AD9783 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO Data Sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9783 (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FS ADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 D0N D0P D1N D1P D2N D2P D3N D3P D4N D4P D10P D10N D9P D9N D8P D8N DCOP DCON DVDD33 DVSS DCIP DCIN D7P D7N D6P D6N D5P D5N 19 20 2
PAGE 10
AD9780/AD9781/AD9783 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.4 1.5 0.2 1.0 0 0.5 –0.2 –0.4 LSB LSB 0 –0.5 –0.6 –0.8 –1.0 –1.0 –1.5 –1.2 –2.0 16,384 32,768 49,152 65,535 CODE –1.6 06936-005 0 0 16,384 32,768 49,152 65,535 CODE Figure 5. AD9783 INL, TA = 85°C, FS = 20 mA 06936-008 –1.4 –2.5 Figure 8. AD9783 DNL, TA = 85°C, FS = 20 mA 5 0.4 4 0.2 0 3 –0.2 –0.4 LSB LSB 2 1 –0.6 –0.8 0 –1.0 –1 –1.2 –2 16,384 32,768 49,152 65,535 CODE –1.
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Data Sheet AD9780/AD9781/AD9783 0.059 0.4 0.3 0.2 –0.060 0.1 LSB LSB 0 –0.1 –0.179 –0.2 –0.3 –0.297 –0.4 0 4096 8192 12,288 16,383 CODE –0.416 06936-011 –0.6 0 4096 8192 12,288 16,383 CODE Figure 11. AD9781 INL, TA = 85°C, FS = 20 mA 06936-014 –0.5 Figure 14. AD9781 DNL, TA = 85°C, FS = 20 mA 0.1 0.6 0.4 0 0.2 –0.1 LSB LSB 0 –0.2 –0.4 –0.2 –0.3 –0.6 4096 8192 12288 16,383 CODE –0.5 0 0.1 0 0 –0.1 –0.1 LSB 0.1 –0.2 –0.3 –0.4 –0.4 –0.5 –0.
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AD9780/AD9781/AD9783 Data Sheet 90 100 85 95 90 80 250MSPS 85 SFDR (dBc) 70 65 60 70 65 +85°C 60 500MSPS 55 50 50 45 50 100 150 200 250 300 350 400 450 500 fOUT (MHz) 40 06936-017 0 0 25 50 75 100 125 150 175 200 225 250 fOUT (MHz) Figure 17. AD9783 SFDR vs. fOUT Over fDAC in Baseband and Mix Modes, FS = 20 mA 06936-020 45 40 Figure 20. AD9783 SFDR vs.
PAGE 13
Data Sheet AD9780/AD9781/AD9783 100 –140 95 –143 –6dBFS 90 –146 –3dBFS 85 –149 NSD (dBm/Hz) IMD (dBc) 80 75 70 0dBFS 65 –152 –155 250MSPS –158 60 –161 55 –164 45 0 30 60 90 120 150 180 210 240 fOUT (MHz) –170 06936-023 40 0 50 100 150 200 250 300 350 400 450 500 fOUT (MHz) Figure 23. AD9783 IMD vs. fOUT Over Digital Input Level, TA = 25°C, at 500 MSPS, FS = 20 mA Figure 26. AD9783 Eight-Tone NSD vs.
PAGE 14
Data Sheet –50 –50 –55 –55 –60 –60 245.76MSPS –70 –75 –3dB –75 –80 –85 –85 0 100 200 300 400 500 fOUT (MHz) Figure 29. AD9783 ACLR for First Adjacent Band One-Carrier W-CDMA Baseband and Mix Modes, FS = 20 mA –90 –55 –60 –60 –65 –65 ACLR (dBc) –55 491.52MSPS –75 100 200 300 400 500 Figure 32. AD9783 ACLR for First Adjacent Channel Two-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA –50 245.
PAGE 15
Data Sheet AD9780/AD9781/AD9783 –50 1.0 0.5 –55 0 –0.5 0dB AMPLITUDE (dBm) ACLR (dBc) –60 –65 –70 –3dB –75 –80 –1.0 NORMAL MODE –1.5 –2.0 –2.5 –3.0 MIX MODE –3.5 –4.0 –85 200 300 400 500 fOUT (MHz) Figure 35. AD9783 ACLR for First Adjacent Channel Four-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA 0.8 –55 0.6 –60 0.4 LSB 0dB –75 240 300 360 420 480 540 600 –0.2 –0.4 –85 –0.6 100 180 0 –80 0 120 0.
PAGE 16
AD9780/AD9781/AD9783 Data Sheet 100 –50 95 –55 90 85 –60 FIRST ADJACENT CHANNEL 75 70 65 60 55 –65 –70 –75 SECOND ADJACENT CHANNEL –85 45 0 50 100 150 200 250 300 350 400 450 500 fOUT (MHz) –90 06936-041 40 THIRD ADJACENT CHANNEL –80 50 0 100 200 300 400 500 fOUT (MHz) Figure 41. AD9781 SFDR vs. fOUT in Baseband and Mix Modes, at 500 MSPS, FS = 20 mA 06936-044 ACLR (dBc) SFDR (dBc) 80 Figure 44. AD9781 ACLR for One-Carrier W-CDMA Baseband and Mix Modes, at 491.
PAGE 17
Data Sheet AD9780/AD9781/AD9783 100 –140 95 –142 –144 –146 85 –148 80 –150 NSD (dBm/Hz) SFDR (dBc) 90 75 70 65 1-TONE –152 –154 –156 –158 60 –160 55 –162 8-TONE –164 50 –166 45 50 100 150 200 250 300 350 400 450 500 fOUT (MHz) –170 0 50 100 150 200 250 300 350 400 450 500 fOUT (MHz) Figure 47. AD9780 SFDR vs. fOUT in Baseband and Mix Modes, at 500 MSPS, FS = 20 mA 06936-049 –168 0 06936-047 40 Figure 49. AD9780 One-Tone, Eight-Tone NSD vs.
PAGE 18
AD9780/AD9781/AD9783 Data Sheet TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.
PAGE 19
Data Sheet AD9780/AD9781/AD9783 THEORY OF OPERATION The AD9780/AD9781/AD9783 have a combination of features that make them very attractive for wired and wireless communications systems. The dual DAC architecture facilitates easy interface to common quadrature modulators when designing single sideband transmitters. In addition, the speed and performance of the devices allow wider bandwidths and more carriers to be synthesized than in previously available products.
PAGE 20
AD9780/AD9781/AD9783 Data Sheet Bits[4:0], A4, A3, A2, A1, and A0, determine which register is accessed during the data transfer of the communication cycle. For multibyte transfers, this address is a starting or ending address depending on the current data transfer mode. For MSB-first format, the specified address is an ending address or the most significant address in the current cycle.
PAGE 21
Data Sheet AD9780/AD9781/AD9783 SPI REGISTER MAP Table 11.
PAGE 22
AD9780/AD9781/AD9783 Data Sheet SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 12.
PAGE 23
Data Sheet Register AUXDAC1 AD9780/AD9781/AD9783 Address 0x0D 0x0E Bit 7:0 1:0 Name AUXDAC1[9:0] DAC2 FSC 0x0F 0x10 7:0 1:0 DAC2FSC[9:0] AUXDAC2 0x11 0x12 7:0 1:0 AUXDAC2[9:0] 0x12 7 AUX2SGN 6 AUX2DIR 7 6 5 7:0 7:0 7:0 7:0 7:4 3:0 BISTEN BISTRD BISTCLR BISTRES1[15:0] Function AUXDAC1 output current adjustment word. 0x3FF, sets AUXDAC1 output current to 2.0 mA. 0x200, sets AUXDAC1 output current to 1.0 mA. 0x000, sets AUXDAC1 output current to 0.0 mA. 0, AUX1P output pin is active.
PAGE 24
AD9780/AD9781/AD9783 Data Sheet SPI PORT, RESET, AND PIN MODE In general, when the AD9780/AD9781/AD9783 are powered up, an active high pulse applied to the RESET pin should follow. This ensures the default state of all control register bits. In addition, once the RESET pin goes low, the SPI port can be activated; thus, CSB should be held high.
PAGE 25
Data Sheet AD9780/AD9781/AD9783 PARALLEL DATA PORT INTERFACE As diagrammed in Figure 56, the incoming LVDS data is latched by an internally generated clock referred to as the data sampling signal (DSS). DSS is a delayed version of the main DAC clock signal, CLKP/CLKN. Optimal positioning of the rising and falling edges of DSS with respect to the incoming data signals results in the most robust transmission of the DAC data.
PAGE 26
AD9780/AD9781/AD9783 Data Sheet Building the Array The following procedure is used to build the array: 1. 2. 3. 4. 5. 6. Set the values of SMP, SET, and HLD to 0. Read and record the value of the SEEK bit. With SMP and SET set to 0, increment the HLD value until the SEEK bit toggles, and then record the HLD value. This measures the hold time as shown in Figure 57. With SMP and HLD set to 0, increment the SET value until the SEEK bit toggles, and then record the SET value.
PAGE 27
Data Sheet AD9780/AD9781/AD9783 DRIVING THE CLK INPUT The CLK input requires a low jitter differential drive signal. It is a PMOS input differential pair powered from the 1.8 V supply; therefore, it is important to maintain the specified 400 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 1 V p-p about the 400 mV common-mode voltage. CLK can be driven by an offset ac-coupled signal, as shown in Figure 59. V1: 296mV V2: –228mV ΔV: –524mV 1 0.
PAGE 28
AD9780/AD9781/AD9783 Data Sheet FULL-SCALE CURRENT GENERATION The current output appearing at IOUTP and IOUTN is a function of both the input code, and IFS and can be expressed as Internal Reference Full-scale current on the I DAC and Q DAC can be set from 8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is used to set up a current in an external resistor connected to FS ADJ (Pin 54). A simplified block diagram of the reference circuitry is shown in Figure 62.
PAGE 29
Data Sheet AD9780/AD9781/AD9783 In return-to-zero mode, the output is set to midscale every other half clock cycle. The output is similar to the DAC output in normal mode except that the output pulses are half the width and half the area. Because the output pulses have half the width, the sinc function is scaled in frequency by two and has a first null at 2 × fDAC. Because the area of the pulses is half that of the pulses in normal mode, the output power is half the normal mode output power.
PAGE 30
AD9780/AD9781/AD9783 Data Sheet POWER DISSIPATION 0.50 0.45 0.45 0.40 0.40 0.35 0.35 0.30 0.30 0.25 0.20 0.20 0.15 0.15 0.10 0.10 0.05 0.05 0 0 100 200 300 400 500 CLOCK SPEED (MSPS) 0 0 100 200 300 400 500 CLOCK SPEED (MSPS) Figure 68. Power Dissipation, I Data Only, Single DAC Mode Figure 71. Power Dissipation, I and Q Data, Dual DAC Mode 0.200 0.200 0.175 0.175 0.150 0.150 0.125 0.125 POWER (W) POWER (W) 0.25 06936-068 POWER (W) 0.
PAGE 31
Data Sheet AD9780/AD9781/AD9783 OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 0.60 0.42 0.24 0.60 0.42 0.24 55 54 72 1 PIN 1 INDICATOR PIN 1 INDICATOR 9.85 9.75 SQ 9.65 TOP VIEW 0.50 BSC 4.70 BSC SQ EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 SEATING PLANE 0.80 MAX 0.65 TYP 12° MAX 8.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.23 0.18 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 32
AD9780/AD9781/AD9783 Data Sheet NOTES ©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06936-0-6/12(B) Rev.