Datasheet

AD9776/AD9778/AD9779
Rev. A | Page 6 of 56
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
S
OUTF
I
Table 2. AD9776, AD9778, and AD9779 Digital Specifications
Parameter Conditions Min Typ Max Unit
CMOS INPUT LOGIC LEVEL
Input V
IN
Logic High 2.0 V
Input V
IN
Logic Low 0.8 V
Maximum Input Data Rate at Interpolation
1× 300 MSPS
2× 250 MSPS
4× 200 MSPS
8× 125 MSPS
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)
1
Output V
OUT
Logic High 2.4 V
Output V
OUT
Logic Low 0.4 V
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) SYNC_I+ = V
IA
, SYNC_I− = V
IB
Input Voltage Range, V
IA
or V
IB
825 1575 mV
Input Differential Threshold, V
IDTH
−100 +100 mV
Input Differential Hysteresis, V
IDTHH
− V
IDTHL
20 mV
Receiver Differential Input Impedance, R
IN
2
80 120 Ω
LVDS Input Rate 125 MSPS
Set-Up Time, SYNC_I to DAC Clock −0.2 ns
Hold Time, SYNC_I to DAC Clock 1 ns
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = V
OA
, SYNC_O− = V
OB
, 100 Ω termination
Output Voltage High, V
OA
or V
OB
825 1575 mV
Output Voltage Low, V
OA
or V
OB
1025 mV
Output Differential Voltage, |V
OD
| 150 200 250 mV
Output Offset Voltage, V
OS
1150 1250 mV
Output Impedance, R
O
Single-ended 80 100 120 Ω
Maximum Clock Rate 1 GHz
DAC CLOCK INPUT (CLK+, CLK−)
Differential Peak-to-Peak Voltage (CLK+, CLK−)
3
400 800 2000 mV
Common-Mode Voltage 300 400 500 mV
Maximum Clock Rate
4
1 GSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 40 MHz
Minimum Pulse Width High 12.5 ns
Minimum Pulse Width Low 12.5 ns
1
Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load; maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests
using an external buffer for this signal.
2
Guaranteed at 25°C. Can drift above 120 Ω at temperatures above 25°C.
3
When using the PLL, a differential swing of 2 V p-p is recommended.
4
Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V.