Datasheet

AD9776/AD9778/AD9779

Rev. A | Page 45 of 56

In addition to this divisor function, DATACLK can be divided

by up to an additional factor of 4, according to the state of the

DATACLK divide register (Register 0x03, Bits<5:4>). For more

details, see

Table 2 2).

Table 22. Extra DATACLK Divisor Ratio

00 1

01 2

10 4

11 1

The maximum divisor resulting from the combination of the

values in

Table 2 1, and the DATACLK divide register is 32.

Manual Input Timing Correction

Correction of input timing can be achieved manually. The

correction function is controlled by Register 0x03, Bits<7:6>.

The function is programmed as shown in

Table 23 .

Table 23. Input Timing Correction Mode

00 Error check disabled

01 Reserved

10 Reserved

11 Reserved

Necessary corrections can be made by adjusting DATACLK

delay and the DATACLK invert bit (Register 2, Bit 2).

DATACLK delay can then be swept to find the range over which

the timing is valid. The final value for data delay should be the

value that corresponds to the middle of the valid timing range.

If a valid timing range is not found during this sweep, the user

should invert the DATACLK invert bit and repeat the process.

Multiple DAC Synchronization

The AD9779 has programmable features that allow the CMOS

digital data bus inputs and internal filters on multiple devices to

be synchronized. This means that the DATACLK output signal

on one AD9779 can be used to register the output data for a data

bus delivering data to multiple AD9779s. The details of this opera-

tion are given in the Analog Devices Application Note AN-822.