Datasheet

AD9776/AD9778/AD9779
Rev. A | Page 3 of 56
FUNCTIONAL BLOCK DIAGRAM
10
10
10
10
CLOCK GENERATION/DISTRIBUTION
DATA
ASSEMBLER
DIGITAL CONTROLLER
2× 2×
SYNC
1
CLOCK
MULTIPLIER
2×/4×/8×
16-BIT
IDAC
CLK+
CLK–
IOUT1_P
IOUT1_N
AUX1_P
AUX1_N
AUX2_P
AUX2_N
IOUT2_P
IOUT2_N
GAIN
GAIN
GAIN
GAIN
16-BIT
QDAC
2×
SYNC
1
I
LATCH
DELAY
LINE
Q
LATCH
P2D(15:0)
P1D(15:0)
SYNC_O
SYNC_I
DATACLK_OUT
2× 2× 2×
n × f
DAC
/8
n = 0, 1, 2 ... 7
POWER-ON
RESET
SDO
SDIO
SCL
K
CSB
SERIAL
PERIPHERAL
INTERFACE
COMPLEX
MODULATOR
REFERENCE
AND BIAS
VREF
I120
DELAY
LINE
0
5361-001
Figure 2. Functional Block Diagram