Datasheet

AD9776/AD9778/AD9779
Rev. A | Page 29 of 56
Address
Register Name Reg. No. Bits Description Function Default
Sync Control Register 06 7:4 Sync input delay
See the
Multiple DAC Synchronization
section for details on using these registers
to synchronize multiple DACs
0
06 3:0
Input sync pulse timing error
tolerance
0
07 7 Sync receiver enable 0
07 6 Sync driver enable 0
07 5 Sync triggering edge 0
07 4:0
SYNC_I to input data sampling
clock offset
0
PLL Control 08 7:2 PLL band select
VCO frequency range vs. PLL band select
value (see
Table 18)
111001
08 1:0 VCO AGC gain control
Lower number (low gain) is generally better
for performance
11
09 7 PLL enable
0: PLL off, DAC rate clock supplied by
outside source
0
1: PLL on, DAC rate clock synthesized
internally from external reference clock via
PLL clock multiplier
09 6:5 PLL VCO divide ratio FVCO/f
DAC
00 × 1
01 × 2
10 × 4
11 × 8
09 4:3 PLL loop divide ratio f
DAC
/f
REF
00 × 2
01 × 4
10 × 8
11 × 16
09 2:0 PLL bias setting Always set to 010 010
0A 7:5 PLL control voltage range
000 to 111, proportional to voltage at PLL
loop filter output, readback only
Misc Control
0A 4:0 PLL loop bandwidth adjustment
See
PLL Loop Filter Bandwidth section for
details
I DAC Control Register 0B 7:0 I DAC gain adjustment
(7:0) LSB slice of 10-bit gain setting word
for I DAC
11111001
0C 7 I DAC sleep 0: I DAC on 0
1: I DAC off
0C 6 I DAC power-down 0: I DAC on 0
1: I DAC off
0C 1:0 I DAC gain adjustment
(9:8) MSB slice of 10-bit gain setting word
for I DAC
01
0D 7:0 Aux DAC1 gain adjustment
(7:0) LSB slice of 10-bit gain setting word for
Aux DAC1
00000000
0E 7 Aux DAC1 sign 0: positive
1: negative
0E 6 Aux DAC1 current direction 0: source 0
1: sink
0E 5 Aux DAC1 power-down 0: Aux DAC1 on 0
1: Aux DAC1 off
Aux DAC1 Control
Register
0E 1:0 Aux DAC1 gain adjustment
(9:8) MSB slice of 10-bit gain setting word
for Aux DAC1
00