Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) TQFP 100 EP

Dual 12-/14-/16-Bit,

1 GSPS, Digital-to-Analog Converters

AD9776/AD9778/AD9779

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,

full operating conditions

SFDR = 78 dBc to f

OUT

= 100 MHz

Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF

Analog output: adjustable 8.7 mA to 31.7 mA,

= 25 Ω to 50 Ω

Novel 2×, 4×, and 8× interpolator/coarse complex modulator

allows carrier placement anywhere in DAC bandwidth

Auxiliary DACs allow control of external VGA and offset control

Multiple chip synchronization interface

High performance, low noise PLL clock multiplier

Digital inverse sinc filter

100-lead, exposed paddle TQFP package

APPLICATIONS

Wireless infrastructure

WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM

Digital high or low IF synthesis

Internal digital upconversion capability

Transmit diversity

Wideband communications: LMDS/MMDS, point-to-point

GENERAL DESCRIPTION

The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high

dynamic range, digital-to-analog converters (DACs) that pro-

vide a sample rate of 1 GSPS, permitting multicarrier generation

up to the Nyquist frequency. They include features optimized

for direct conversion transmit applications, including complex

digital modulation, and gain and offset compensation. The DAC

outputs are optimized to interface seamlessly with analog quad-

rature modulators such as the AD8349. A serial peripheral interface

(SPI®) provides for programming/readback of many internal

parameters. Full-scale output current can be programmed over a

range of 10 mA to 30 mA. The devices are manufactured on an

advanced 0.18 m CMOS process and operate on 1.8 V and

3.3 V supplies for a total power consumption of 1.0 W. They are

enclosed in 100-lead TQFP packages.

PRODUCT HIGHLIGHTS

1. Ultralow noise and intermodulation distortion (IMD)

enable high quality synthesis of wideband signals from

baseband to high intermediate frequencies.

2. A proprietary DAC output switching technique enhances

dynamic performance.

3. The current outputs are easily configured for various

single-ended or differential circuit topologies.

4. CMOS data input interface with adjustable set up and hold.

5. Novel 2×, 4×, and 8× interpolator/coarse complex

modulator allows carrier placement anywhere in DAC

bandwidth.

TYPICAL SIGNAL CHAIN

05361-114

FPGA/ASIC/DSP

COMPLEX I AND Q

QUADRATURE

MODULATOR/

MIXER/

AMPLIFIER

I DAC

Q DAC

DIGITAL INTERPOLATION FILTERS

AD9779

POST DAC

ANALOG FILTER

Figure 1.

Summary of content (56 pages)

PAGE 1
Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters AD9776/AD9778/AD9779 FEATURES GENERAL DESCRIPTION Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions SFDR = 78 dBc to fOUT = 100 MHz Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.
PAGE 2
AD9776/AD9778/AD9779 TABLE OF CONTENTS Features .............................................................................................. 1 SPI Register Map ............................................................................ 27 Applications....................................................................................... 1 Interpolation Filter Architecture .................................................. 31 General Description ........................................................
PAGE 3
AD9776/AD9778/AD9779 FUNCTIONAL BLOCK DIAGRAM DELAY LINE CLOCK GENERATION/DISTRIBUTION SYNC_I DATACLK_OUT CLOCK MULTIPLIER 2×/4×/8× DELAY LINE DATA ASSEMBLER SYNC1 2× 2× 2× n × fDAC /8 n = 0, 1, 2 ...
PAGE 4
AD9776/AD9778/AD9779 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1.
PAGE 5
AD9776/AD9778/AD9779 Parameter 8× Mode, fDAC/4 Modulation, fDAC = 1 GSPS, IF = 262.5 MHz Power-Down Mode Power Supply Rejection Ratio, AVDD33 OPERATING RANGE 1 Min AD9776 Typ Max 980 2 −0.3 −40 +25 Min 3.7 +0.3 −0.3 +85 −40 AD9778 Typ Max 980 2 Based on a 10 kΩ external resistor. Rev. A | Page 5 of 56 +25 Min 3.7 +0.3 −0.3 +85 −40 AD9779 Typ Max 980 Unit mW 2 3.7 +0.
PAGE 6
AD9776/AD9778/AD9779 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2.
PAGE 7
AD9776/AD9778/AD9779 DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. AD9776, AD9778, and AD9779 Digital Input Data Timing Specifications Parameter INPUT DATA (ALL MODES, −40°C to +85°C) 1 Set-Up Time, Input Data to DATACLK Hold Time, Input Data to DATACLK Set-Up Time, Input Data to REFCLK Hold Time, Input Data to REFCLK 1 Min Typ Max +2.5 −0.4 −0.8 +2.9 Unit ns ns ns ns Timing vs. temperature and data valid keep out windows are delineated in Table 19. AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.
PAGE 8
AD9776/AD9778/AD9779 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD33, DVDD33 DVDD18, CVDD18 AGND DGND CGND I120, VREF, IPTAT IOUT1-P, IOUT1-N, IOUT2-P, IOUT2-N, Aux1-P, Aux1-N, Aux2-P, Aux2-N P1D15 to P1D0, P2D15 to P2D0 DATACLK, TXENABLE CLK+, CLK− RESET, IRQ, PLL_LOCK, SYNC_O+, SYNC_O−, SYNC_I+, SYNC_I−, CSB, SCLK, SDIO, SDO Junction Temperature Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 9
AD9776/AD9778/AD9779 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 PIN 1 2 CGND 3 ANALOG DOMAIN 75 I120 74 VREF 73 IPTAT CGND 4 72 AGND CLK+ 5 71 IRQ CLK– 6 70 RESET CGND 7 69 CSB CGND 8 68 SCLK DIGITAL DOMAIN CVDD18 9
PAGE 10
AD9776/AD9778/AD9779 Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Mnemonic TXENABLE P2D<11> P2D<10> P2D<9> DVDD18 DGND P2D<8> P2D<7> P2D<6> P2D<5> P2D<4> P2D<3> P2D<2> P2D<1> DVDD18 DGND P2D<0> NC NC NC NC DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK CSB RESET IRQ AGND Description Transmit Enable. Port 2, Data Input D11 (MSB). Port 2, Data Input D10. Port 2, Data Input D9. 1.8 V Digital Supply. Digital Common.
PAGE 11
AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 AD9776/AD9778/AD9779 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 PIN 1 2 CGND 3 ANALOG DOMAIN 75 I120 74 VREF 73 IPTAT CGND 4 72 AGND CLK+ 5 71 IRQ CLK– 6 70 RESET CGND 7 69 CSB CGND 8 68 SCLK DIGITAL DOMAIN CVDD18 9 AD9778 67 SDIO CVDD18 10 TOP VIEW (Not
PAGE 12
AD9776/AD9778/AD9779 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Mnemonic P2D<12> P2D<11> DVDD18 DGND P2D<10> P2D<9> P2D<8> P2D<7> P2D<6> P2D<5> P2D<4> P2D<3> DVDD18 DGND P2D<2> P2D<1> P2D<0> NC NC DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK CSB RESET IRQ AGND IPTAT Description Port 2, Data Input D12. Port 2, Data Input D11. 1.8 V Digital Supply. Digital Common. Port 2, Data Input D10. Port 2, Data Input D9.
PAGE 13
AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 AD9776/AD9778/AD9779 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 75 I120 74 VREF 73 IPTAT 4 72 AGND CLK+ 5 71 IRQ CLK– 6 70 RESET CGND 7 69 CSB CGND 8 68 SCLK CVDD18 9 AD9779 67 SDIO TOP VIEW (Not to Scale) 66 SDO 65 PLL_LOCK AGND 12 64 DGND SYNC_I+ 13
PAGE 14
AD9776/AD9778/AD9779 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Mnemonic DVDD18 DGND P2D<12> P2D<11> P2D<10> P2D<9> P2D<8> P2D<7> P2D<6> P2D<5> DVDD18 DGND P2D<4> P2D<3> P2D<2> P2D<1> P2D<0> DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SPI_SDO SPI_SDIO SCLK SPI_CSB RESET IRQ AGND IPTAT Description 1.8 V Digital Supply. Digital Common. Port 2, Data Input D12. Port 2, Data Input D11. Port 2, Data Input D10. Port 2, Data Input D9.
PAGE 15
AD9776/AD9778/AD9779 TYPICAL PERFORMANCE CHARACTERISTICS 4 100 3 fDATA = 160MSPS 2 90 fDATA = 200MSPS 0 SFDR (dBc) INL (16-BIT LSB) 1 –1 –2 80 70 fDATA = 250MSPS –3 –4 60 0 10k 20k 30k 40k 50k 50 05361-005 –6 60k CODE 0 20 40 60 80 100 fOUT (MHz) Figure 6. AD9779 Typical INL 05361-008 –5 Figure 9. AD9779 In-Band SFDR vs. fOUT, 2× Interpolation 100 1.5 fDATA = 200MSPS fDATA = 100MSPS 1.0 90 SFDR (dBc) DNL (16-BIT LSB) 0.5 0 –0.5 80 fDATA = 150MSPS 70 –1.
PAGE 16
AD9776/AD9778/AD9779 100 100 90 90 PLL OFF PLL ON SFDR (dBc) fDATA = 200MSPS 70 fDATA = 250MSPS 50 0 20 40 60 80 80 70 60 100 fOUT (MHz) 50 0 10 20 30 40 fOUT (MHz) Figure 12. AD9779 Out-of-Band SFDR vs. fOUT, 2× Interpolation 05361-014 60 05361-011 SFDR (dBc) fDATA = 160MSPS 80 Figure 15.
PAGE 17
AD9776/AD9778/AD9779 100 100 fDATA = 160MSPS fDATA = 200MSPS 90 fDATA = 250MSPS 80 IMD (dBc) IMD (dBc) 90 70 80 fDATA = 75MSPS 70 fDATA = 100MSPS 450 fOUT (MHz) Figure 18. AD9779 Third-Order IMD vs. fOUT, 1× Interpolation Figure 21. AD9779 Third-Order IMD vs.
PAGE 18
AD9776/AD9778/AD9779 100 95 90 EXT REF DC COUPLED 0dBFS 85 –3dBFS 80 75 LGAV 51 W1 S2 S3 FC AA £(f): FTUN SWP –6dBFS 70 65 60 50 0 40 80 120 160 200 240 280 320 360 400 fOUT (MHz) 05361-117 55 START 1.0MHz *RES BW 20kHz 05361-024 IMD (dBc) *ATTEN 20dB REF 0dBm *PEAK Log 10dB/ STOP 400.0MHz SWEEP 1.203s (601 pts) VBW 20kHz Figure 27. AD9779 Two-Tone Spectrum, 4× Interpolation, fDATA = 100 MSPS, fOUT = 30 MHz, 35 MHz Figure 24. IMD Performance vs.
PAGE 19
AD9776/AD9778/AD9779 –150 –55 –60 –154 –158 ACLR (dBc) NSD (dBm/Hz) –65 fDAC = 200MSPS fDAC = 400MSPS –162 fDAC = 800MSPS –70 0dBFS – PLL ON –75 –6dBFS –80 –3dBFS –166 –85 40 60 80 100 fOUT (MHz) 05361-027 20 0 –90 –55 –60 –60 0dBFS – PLL ON 60 80 100 120 140 160 180 200 220 240 260 –65 –3dBFS ACLR (dBc) ACLR (dBc) 40 Figure 32. AD9779 ACLR for Second Adjacent Band WCDMA, 4× Interpolation, fDATA = 122.88 MSPS.
PAGE 20
AD9776/AD9778/AD9779 1.5 *ATTEN 4dB REF –25.28dBm *AVG Log 10dB/ 1.0 INL (14-BIT LSB) EXT REF 0.5 0 –0.5 –1.5 VBW 300kHz RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz 10.00MHz –12.49dBm/ 15.00MHz 3.84000MHz SPAN 50MHz SWEEP 162.2ms (601 pts) 3.840MHz 3.840MHz 3.840MHz LOWER dBm dBc –76.75 –89.23 –80.94 –93.43 –79.95 –92.44 UPPER dBm dBc –77.42 –89.91 –80.47 –92.96 –78.96 –91.45 0 2k 6k 8k 10k CODE Figure 34. AD9779 WCDMA Signal, 4× Interpolation, fDATA =122.
PAGE 21
AD9776/AD9778/AD9779 *ATTEN 4dB REF –25.39dBm *AVG Log 10dB/ 100 90 IMD (dBc) 4× 150MSPS 80 4× 200MSPS 70 4× 100MSPS PAVG 10 W1 S2 CENTER 143.88MHz *RES BW 30kHz 0 40 80 120 160 200 240 280 320 360 400 fOUT (MHz) 05361-035 RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz –12.74dBm/ 10.00MHz 3.84000MHz 15.00MHz 100 LOWER dBc dBm –76.49 –89.23 –80.13 –92.87 –80.90 –93.64 UPPER dBc dBm –76.89 –89.63 –80.02 –92.76 –79.53 –92.
PAGE 22
AD9776/AD9778/AD9779 0.4 100 0.3 90 fDATA = 160MSPS 0.1 SFDR (dBc) INL (12-BIT LSB) 0.2 0 –0.1 80 fDATA = 250MSPS 70 fDATA = 200MSPS –0.2 60 512 1024 1536 2048 2560 3072 3584 4096 CODE 50 0 60 80 100 250 Figure 47. AD9776 In-Band SFDR, 2× Interpolation 0.20 –55 0.15 –60 0.10 –65 1ST ADJ CHAN 0.05 ACLR (dBc) DNL (12-BIT LSB) 40 fOUT (MHz) Figure 44. AD9776 Typical INL 0 –0.05 –70 3RD ADJ CHAN –75 –80 –0.10 2ND ADJ CHAN –85 –0.
PAGE 23
AD9776/AD9778/AD9779 –150 –150 fDAC = 200MSPS fDAC = 200MSPS –154 –158 NSD (dBm/Hz) NSD (dBm/Hz) fDAC = 400MSPS –154 fDAC = 400MSPS fDAC = 800MSPS –162 –158 fDAC = 800MSPS –162 –166 0 10 20 30 40 50 60 70 80 90 100 fOUT (MHz) –170 0 10 20 30 40 50 60 70 80 90 fOUT (MHz) Figure 50. AD9776 Noise Spectral Density vs. fDAC, Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS Figure 51. AD9776 Noise Spectral Density vs.
PAGE 24
AD9776/AD9778/AD9779 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases.
PAGE 25
AD9776/AD9778/AD9779 THEORY OF OPERATION The AD9776/AD9778/AD9779 combine many features that make them very attractive DACs for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common quadrature modulators when designing single sideband transmitters. The speed and performance of the parts allow wider bandwidths and more carriers to be synthesized than in previously available DACs.
PAGE 26
AD9776/AD9778/AD9779 For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the device based on the LSB-first bit (Register 0x00, Bit 6). Table 10. Byte Transfer Count Description Transfer one byte Transfer three bytes Transfer two bytes Transfer four bytes The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first mode is active.
PAGE 27
AD9776/AD9778/AD9779 SPI REGISTER MAP Table 11.
PAGE 28
AD9776/AD9778/AD9779 Table 12. SPI Register Description Register Name Comm Register Digital Control Register Sync Control Register Address Reg. No.
PAGE 29
AD9776/AD9778/AD9779 Register Name Sync Control Register PLL Control Misc Control I DAC Control Register Aux DAC1 Control Register Address Reg. No.
PAGE 30
AD9776/AD9778/AD9779 Register Name Q DAC Control Register Aux DAC2 Control Register Interrupt Register Address Reg. No.
PAGE 31
AD9776/AD9778/AD9779 INTERPOLATION FILTER ARCHITECTURE Integer Value −4 0 +13 0 −34 0 +72 0 −138 0 +245 0 −408 0 +650 0 −1003 0 +1521 0 −2315 0 +3671 0 −6642 0 +20,755 +32,768 Upper Coefficient H(23) H(22) H(21) H(20) H(19) H(18) H(17) H(16) H(15) H(14) H(13) Integer Value −39 0 +273 0 −1102 0 +4964 +8192 Table 16.
PAGE 32
AD9776/AD9778/AD9779 10 0 –10 –10 –20 –20 –30 –40 –50 –60 –30 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 –4 –3 –2 –1 0 1 2 3 4 fOUT (× Input Data Rate) –100 –4 Figure 59. 8× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off) –3 –2 –1 0 1 2 3 4 fOUT (× Input Data Rate) 05361-059 ATTENUATION (dB) 0 05361-056 ATTENUATION (dB) 10 Figure 62.
PAGE 33
AD9776/AD9778/AD9779 10 Shifted mode filter responses allow the pass band to be centered around ±0.5 fDATA, ±1.5 fDATA, ±2.5 fDATA, and ±3.5 fDATA. Switching to the shifted mode response does not modulate the signal. Instead, the pass band is simply shifted. For example, picture the response shown in Figure 67 and assume the signal in-band is a complex signal over the bandwidth 3.2 fDATA to 3.3 fDATA. If the even mode filter response is then selected, the pass band becomes centered at 3.5 fDATA.
PAGE 34
AD9776/AD9778/AD9779 Table 17.
PAGE 35
AD9776/AD9778/AD9779 –3 –2 –1 0 2 ASSUMING 8× INTERPOLATION –30 SHIFTED –3 × fDAC/8 SHIFTED –fDAC/4 SHIFTED –fDAC/8 1 fOUT (× Input Data Rate), 3 4 05361-067 –80 –4 +fDAC/2 +fDAC/4 +fDAC/8 BASEBAND –fDAC/8 –70 –fDAC/4 SHIFTED –DC –50 0 –20 SHIFTED –DC –40 SHIFTED –fDAC/8 –30 –60 –fDAC/2 ATTENUATION (dB) –20 10 –10 Figure 70.
PAGE 36
AD9776/AD9778/AD9779 0.1μF PLL Enabled (Register 0x09, Bit 7 = 1) CLK+ 50Ω VCM = 400mV CLK– 0.1μF 05361-068 50Ω LVDS_N_IN Figure 71. LVDS REFCLK Drive Circuit If a clean sine clock is available, it can be transformer-coupled to REFCLK, as shown in Figure 71. Use of a CMOS or TTL clock is also acceptable for lower sample rates. It can be routed through a CMOS to LVDS translator, then ac-coupled, as described in this section.
PAGE 37
AD9776/AD9778/AD9779 Table 18. VCO Frequency Range vs.
PAGE 38
AD9776/AD9778/AD9779 (Register 0x09, Bits<2:0>) should be set to 111. The PLL control voltage (Register 0x0A, Bits<7:5>) is read back and is proportional to the dc voltage at the internal loop filter output. With the PLL bias settings given in this section, the readback from the PLL control voltage should typically be 010, or possibly 001 or 011. Anything outside of this range indicates that the PLL is not operating correctly.
PAGE 39
AD9776/AD9778/AD9779 0.7 8× INTERPOLATION 0.6 4× INTERPOLATION 0.5 2× INTERPOLATION, ZERO STUFFING 0.4 2× INTERPOLATION 0.3 1× INTERPOLATION, ZERO STUFFING 0.2 1× INTERPOLATION 0.1 0 0 50 75 100 125 150 175 200 225 250 Figure 81. Total Power Dissipation, I Data Only, Real Mode 0.4 AD9779 AUX DAC1 8× INTERPOLATION POWER (W) 0.1μF AD9779 AUX DAC2 QUAD MOD I INPUTS 4× INTERPOLATION 0.
PAGE 40
AD9776/AD9778/AD9779 0.125 0.075 8× INTERPOLATION, fDAC/8, fDAC/4, fDAC/2, NO MODULATION 0.100 4× INTERPOLATION ALL INTERPOLATION MODES POWER (W) POWER (W) 0.050 0.075 2× INTERPOLATION 0.050 0.025 0.025 25 50 75 100 125 150 175 200 225 250 fDATA (MSPS) Figure 84. Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation Modes and Zero Stuffing 1.0 0.9 25 50 75 100 125 150 175 200 225 250 Figure 87. Power Dissipation, Clock 1.
PAGE 41
AD9776/AD9778/AD9779 POWER-DOWN AND SLEEP MODES INTERLEAVED DATA MODE The AD977x has a variety of power-down modes, so that the digital engine, main TxDACs, or auxiliary DACs can be powered down individually or together. Via the SPI port, the main TxDACs can be placed in sleep or power-down mode. In sleep mode, the TxDAC output is turned off, thus reducing power dissipation. The reference remains powered on, however, so that recovery from sleep mode is very fast.
PAGE 42
AD9776/AD9778/AD9779 REFERENCE CLOCK IN tSREFCLK tSDATACLK tHREFCLK tHDATACLK INPUT DATA 05361-120 DATA CLOCK OUT Figure 92. Timing Specifications, PLL Enabled or Disabled, Interpolation = 1× SYNC_IN tH_SYNC tS_SYNC REFERENCE CLOCK IN DATA CLOCK OUT tSDATACLK tHDATACLK INPUT DATA 05361-121 tHREFCLK tSREFCLK Figure 93.
PAGE 43
AD9776/AD9778/AD9779 and must be no greater than DATACLK for proper synchronization. There is no limit on how slow the SYNC_I signal can be driven. As long as the set up and hold timing relationship between SYNC_I and REFCLK given in Table 19 is met, the input data is latched on the immediate next rising edge of REFCLK. Note that a rising edge of DATACLK out occurs concurrently with the next REFCLK rising edge, after a short propagation delay.
PAGE 44
AD9776/AD9778/AD9779 TEK RUN: 5.00GS/s To meet strict timing requirements at input data rates of up to 250 MSPS, the AD977x has a fine timing feature. Fine timing adjustments are made by programming values into the data clock delay register (Register 0x04, Bits<7:4>). This register can be used to add delay between the REFCLK in and the DATACLK out. Figure 97 shows the default delay present when DATACLK delay is disabled. The disable function bit is found in Register 0x02, Bit 4.
PAGE 45
AD9776/AD9778/AD9779 In addition to this divisor function, DATACLK can be divided by up to an additional factor of 4, according to the state of the DATACLK divide register (Register 0x03, Bits<5:4>). For more details, see Table 22). Table 22. Extra DATACLK Divisor Ratio Register 0x03, Bits<5:4> 00 01 10 11 Divider Ratio 1 2 4 1 Necessary corrections can be made by adjusting DATACLK delay and the DATACLK invert bit (Register 2, Bit 2).
PAGE 46
AD9776/AD9778/AD9779 EVALUATION BOARD OPERATION The AD977x evaluation board is designed to optimize the DAC performance and the speed of the digital interface, yet remains user friendly. To operate the board, the user needs a power source, a clock source, and a digital data source. The user also needs a spectrum analyzer or an oscilloscope to look at the DAC output. The diagram in Figure 100 illustrates the test setup. A sine or square wave clock works well as a clock source.
PAGE 47
AD9776/AD9778/AD9779 1. SET INTERPOLATION RATE 2. SET INTERPOLATION FILTER MODE 3. SET INPUT DATA FORMAT 05361-099 4. SET DATACLK POLARITY TO MATCH INPUT TIMING Figure 102. SPI Port Software Window The default settings for the evaluation board allow the user to view the differential outputs through a transformer that converts the DAC output signal to a single-ended signal. On the evaluation board, these transformers are designated T1A, T2A, T3A, and T4A.
PAGE 48
AD9776/AD9778/AD9779 MODIFYING THE EVALUATION BOARD TO USE THE AD8349 ON-BOARD QUADRATURE MODULATOR The evaluation board contains an Analog Devices AD8349 quadrature modulator. The AD977x and AD8349 provide an easy-to-interface DAC/modulator combination that can be easily evaluated on the evaluation board.
PAGE 49
Figure 104. Evaluation Board, Rev. D, Power Supply Decoupling and SPI Interface Rev. A | Page 49 of 56 DPWR33_IN TP7 RED DVDD33_IN TP6 RED AVDD33_IN TP5 RED DVDD18_IN 05361-101 C77 22μF 16V C22 22μF 16V C21 22μF 16V C20 22μF 16V C76 22μF 16V TP3 RED CVDD18_IN + + + + + TP1 RED TP21 RED TP20 RED TP19 RED TP18 RED TP17 RED L6 L7 EXC-CL4532U1 C48 0.1μF L15 EXC-CL4532U1 L5 EXC-CL4532U1 C45 0.1μF L14 EXC-CL4532U1 L4 EXC-CL4532U1 C28 0.
PAGE 50
S2 C55 0.1µF C14 0.1µF C6 4.7µF 2 JP13 TC1-1T C24 1nF C59 1nF C9 0.1µF C1 4.7µF R11 50Ω JP3 AVDD33 C58 1nF DATACLK S7 1 R32 25Ω + + VOLT 4 2 DPWR33 5 C78 VOLT 4.7µF Y VCC 6 D2N JP2 JP8 D1N C18 1nF VOLT C8 10µF R56 10Ω 1 U11 3 GND 2 A 1 NC R64 1kΩ R26 22Ω C84 0.1µF Rev. A | Page 50 of 56 T3A S D2P 4 6 4 P 1 2 JP18 R26 22Ω SN74LVC1G34 C32 0.1µF Figure 105. Evaluation Board, Rev.
PAGE 51
AD9776/AD9778/AD9779 D1N C80 2.1pF R15 20Ω C64 17.2pF R17 150Ω C50 17.2pF L10 55nH AUX1_N R4 150Ω C53 0.1µF R20 40Ω R19 300Ω C81 2.1pF JP13 AUX1_P R12 150Ω C63 17.2pF C52 17.2pF L11 55nH R22 147.5Ω R21 40Ω 3 P C47 100pF 4 S T5 6 ADTL1-12 R16 20Ω 1 D1P VDDM C72 0.1µF QBBP QBBN G4B G4A VPS2 VOUT G3 G2 1 2 3 4 5 6 7 8 J4 DGND2 VDDM U9 2 DGND2 1 2 2 DGND2 IBBP IBBN G1A G1B LOIN LOIP VPS1 ENBL C73 0.
PAGE 52
AD9776/AD9778/AD9779 P4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 P4 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 P4 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 PKG_TYPE = MOLEX110 VAL PKG_TYPE = MOLEX110 VAL PKG_TYPE = MOLEX110 VAL DGND BLK P4 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 P4 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 E15 E16 E17 E18 E19 E20 E21 E22
PAGE 53
05361-107 AD9776/AD9778/AD9779 05361-108 Figure 110. Evaluation Board, Rev. D, Top Silk Screen Figure 111. Evaluation Board, Rev. D, Top Layer Rev.
PAGE 54
05361-109 AD9776/AD9778/AD9779 05361-110 Figure 112. Evaluation Board, Rev. D, Layer 2 Figure 113. Evaluation Board, Rev. D, Layer 3 Rev.
PAGE 55
05361-111 AD9776/AD9778/AD9779 05361-112 Figure 114. Evaluation Board, Rev. D, Bottom Layer Figure 115. Evaluation Board, Rev. D, Bottom Silkscreen Rev.
PAGE 56
AD9776/AD9778/AD9779 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 1 SEATING PLANE 76 76 75 100 1 75 PIN 1 BOTTOM VIEW (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 25 26 0.20 0.09 51 50 25 50 1.05 1.00 0.95 7° 3.5° 0° 0.50 BSC 0.27 0.22 0.17 0.15 0.05 26 6.50 NOM COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2.