Datasheet

AD9776A/AD9778A/AD9779A
Rev. B | Page 6 of 56
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
OUTFs
= 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
CMOS INPUT LOGIC LEVEL
Input V
IN
Logic High 2.0 V
Input V
IN
Logic Low 0.8 V
Maximum Input Data Rate at Interpolation
1× 300 MSPS
2× 250 MSPS
4× 200 MSPS
8× DVDD18, CVDD18 = 1.8 V ± 5% 112.5 MSPS
DVDD18, CVDD18 = 1.9 V ± 5% 125 MSPS
DVDD18, CVDD18 = 2.0 V ± 2% 137.5 MSPS
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)
1
Output V
OUT
Logic High 2.4 V
Output V
OUT
Logic Low 0.4 V
DATACLK Output Duty Cycle At 250 MHz, into 5 pF load 40 50 60 %
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) SYNC_I+ = V
IA
, SYNC_I− = V
IB
Input Voltage Range, V
IA
or V
IB
825 1575 mV
Input Differential Threshold, V
IDTH
−100 +100 mV
Input Differential Hysteresis, V
IDTHH
− V
IDTHL
20 mV
Receiver Differential Input Impedance, R
IN
80 120 Ω
LVDS Input Rate
Additional limits on f
SYNC_I
apply; see description of
Register 0x05, Bits[3:1], in Table 14
250 MSPS
Setup Time, SYNC_I to REFCLK 0.4 ns
Hold Time, SYNC_I to REFCLK 0.55 ns
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = V
OA
, SYNC_O− = V
OB
, 100 Ω termination
Output Voltage High, V
OA
or V
OB
1375 mV
Output Voltage Low, V
OA
or V
OB
1025 mV
Output Differential Voltage, |V
OD
| 150 200 250 mV
Output Offset Voltage, V
OS
1150 1250 mV
Output Impedance, R
O
Single-ended 80 100 120 Ω
DAC CLOCK INPUT (REFCLK+, REFCLK−)
Differential Peak-to-Peak Voltage 400 800 2000 mV
Common-Mode Voltage 300 400 500 mV
Maximum Clock Rate DVDD18, CVDD18 = 1.8 V ± 5%, PLL off 900 MHz
DVDD18, CVDD18 = 1.9 V ± 5%, PLL off 1000 MHz
DVDD18, CVDD18 = 2.0 V ± 2%, PLL off 1100 MHz
DVDD18, CVDD18 = 2.0 V ± 2%, PLL on 250 MHz
1
Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load, with maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests
using an external buffer for this signal.