Datasheet

AD9776A/AD9778A/AD9779A
Rev. B | Page 4 of 56
FUNCTIONAL BLOCK DIAGRAM
10
10
10
10
CLOCK GENERATION/DISTRIBUTION
DATA
ASSEMBLER
DIGITAL CONTROLLER
2× 2×
SINC^-1
CLOCK
MULTIPLIER
2×/4×/8×
16-BIT
I DAC
REFCLK+
REFCLK–
OUT1_P
OUT1_N
AUX1_P
AUX1_N
AUX2_P
AUX2_N
OUT2_P
OUT2_N
GAIN
GAIN
GAIN
GAIN
16-BIT
Q DAC
2×
SINC^-1
I
LATCH
DELAY
LINE
Q
LATCH
P2D[15:0]
P1D[15:0]
SYNC_O
SYNC_I
DATACLK
2× 2× 2×
n × f
DAC
/8
n = 0, 1, 2 ... 7
POWER-ON
RESET
SDO
SDIO
SCL
K
CSB
SERIAL
PERIPHERAL
INTERFACE
COMPLEX
MODULATOR
REFERENCE
AND BIAS
VREF
I120
DELAY
LINE
AD9779A
0
6452-001
Figure 2. AD9779A Functional Block Diagram