Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters AD9776A/AD9778A/AD9779A FEATURES GENERAL DESCRIPTION Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.
AD9776A/AD9778A/AD9779A TABLE OF CONTENTS Features .............................................................................................. 1 Inverse Sinc Filter ....................................................................... 38 Applications ....................................................................................... 1 Sourcing the DAC Sample Clock ................................................. 39 General Description ...........................................................
AD9776A/AD9778A/AD9779A REVISION HISTORY 9/08—Rev. A to Rev. B Changed Serial Peripheral Interface (SPI) to 3-Wire Interface Throughout ................................................................................... 1 Change to Features Section .............................................................. 1 Change to Applications Section ...................................................... 1 Changes to Integral Nonlinearity (INL) Parameter, Table 1 .......
AD9776A/AD9778A/AD9779A FUNCTIONAL BLOCK DIAGRAM DELAY LINE CLOCK GENERATION/DISTRIBUTION SYNC_I DATACLK CLOCK MULTIPLIER 2×/4×/8× DELAY LINE DATA ASSEMBLER SINC^-1 2× 2× 2× n × fDAC /8 n = 0, 1, 2 ...
AD9776A/AD9778A/AD9779A SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted. Table 1.
AD9776A/AD9778A/AD9779A DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2.
AD9776A/AD9778A/AD9779A DIGITAL INPUT DATA TIMING SPECIFICATIONS All modes, −40°C to +85°C. Table 3.
AD9776A/AD9778A/AD9779A AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted. Table 4.
AD9776A/AD9778A/AD9779A ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD33, DVDD33 DVDD18, CVDD18 AGND DGND CGND I120, VREF, IPTAT With Respect To AGND, DGND, CGND AGND, DGND, CGND DGND, CGND AGND, CGND AGND, DGND AGND OUT1_P, OUT1_N, OUT2_P, OUT2_N, AUX1_P, AUX1_N, AUX2_P, AUX2_N P1D[15:0], P2D[15:0] AGND DATACLK, TXENABLE DGND REFCLK+, REFCLK− CGND RESET, IRQ, PLL_LOCK, SYNC_O+, SYNC_O−, SYNC_I+, SYNC_I−, CSB, SCLK, SDIO, SDO Junction Temperature Storage Temperature Range DGND DGND Rating −0.
AD9776A/AD9778A/AD9779A AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 I120 74 VREF 73 IPTAT 4 72 AGND REFCLK+ 5 71 IRQ REFCLK– 6 70 RESET CGND 7 69 CSB CGND 8 68 SCLK CVDD18 9 67 SDIO 66 SDO 65 PLL_LOCK AGND 12 64 DGND
AD9776A/AD9778A/AD9779A Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Mnemonic DVDD18 NC NC NC DATACLK DVDD33 TXENABLE/ IQSELECT P2D11 P2D10 P2D9 DVDD18 DGND P2D8 P2D7 P2D6 P2D5 P2D4 P2D3 P2D2 P2D1 DVDD18 DGND P2D0 NC NC NC NC DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK Description 1.8 V Digital Supply. No Connect. No Connect. No Connect. Data Clock Output. 3.3 V Digital Supply. Transmit Enable.
AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 AD9776A/AD9778A/AD9779A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 I120 74 VREF 73 IPTAT 4 72 AGND REFCLK+ 5 71 IRQ REFCLK– 6 70 RESET CGND 7 69 CSB CGND 8 68 SCLK CVDD18 9 AD9778A 67 SDIO TOP VIEW (Not to Scale) 66 SDO 65 PLL_LOCK AGND 12 64 DGND SYNC_I+ 13
AD9776A/AD9778A/AD9779A Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Mnemonic DATACLK DVDD33 TXENABLE/ IQSELECT P2D13 P2D12 P2D11 DVDD18 DGND P2D10 P2D9 P2D8 P2D7 P2D6 P2D5 P2D4 P2D3 DVDD18 DGND P2D2 P2D1 P2D0 NC NC DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK CSB RESET Description Data Clock Output. 3.3 V Digital Supply. Transmit Enable. In single port mode, this pin also functions as IQSELECT. Port 2, Data Input D13 (MSB).
AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 AD9776A/AD9778A/AD9779A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 1 CVDD18 2 75 I120 74 CGND 3 VREF 73 CGND IPTAT 4 72 AGND REFCLK+ 5 71 IRQ REFCLK– 6 70 RESET CGND 7 69 CSB CGND 8 68 SCLK CVDD18 9 AD9779A 67 SDIO TOP VIEW (Not to Scale) 66 SDO 65 PL
AD9776A/AD9778A/AD9779A Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Mnemonic DATACLK DVDD33 TXENABLE/ IQSELECT P2D15 P2D14 P2D13 DVDD18 DGND P2D12 P2D11 P2D10 P2D9 P2D8 P2D7 P2D6 P2D5 DVDD18 DGND P2D4 P2D3 P2D2 P2D1 P2D0 DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK CSB RESET Description Data Clock Output. 3.3 V Digital Supply. Transmit Enable. In single port mode, this pin also functions as IQSELECT.
AD9776A/AD9778A/AD9779A TYPICAL PERFORMANCE CHARACTERISTICS 100 4 3 fDATA = 160MSPS 90 2 fDATA = 200MSPS 0 SFDR (dBc) INL (16-BIT LSB) 1 –1 –2 80 70 fDATA = 250MSPS –3 60 –4 0 10k 20k 30k 50k 40k 50 06452-005 –6 60k CODE 0 20 40 60 80 100 fOUT (MHz) 06452-008 –5 Figure 9. AD9779A In-Band SFDR vs. fOUT, 2× Interpolation Figure 6. AD9779A Typical INL 100 1.5 fDATA = 200MSPS fDATA = 100MSPS 1.0 90 SFDR (dBc) DNL (16-BIT LSB) 0.5 0 –0.5 80 fDATA = 150MSPS 70 –1.
AD9776A/AD9778A/AD9779A 100 100 90 90 PLL OFF PLL ON SFDR (dBc) fDATA = 200MSPS 70 fDATA = 250MSPS 50 0 20 40 60 80 70 60 100 fOUT (MHz) 50 0 10 20 30 40 fOUT (MHz) Figure 12. AD9779A Out-of-Band SFDR vs. fOUT, 2× Interpolation 06452-014 60 80 06452-011 SFDR (dBc) fDATA = 160MSPS 80 Figure 15. AD9779A In-Band SFDR vs.
AD9776A/AD9778A/AD9779A 100 100 fDATA = 160MSPS fDATA = 200MSPS 90 fDATA = 250MSPS 80 IMD (dBc) IMD (dBc) 90 70 80 fDATA = 75MSPS 70 fDATA = 100MSPS 450 fOUT (MHz) 06452-020 425 400 375 350 325 300 275 250 225 200 175 150 fOUT (MHz) fDATA = 125MSPS 50 125 120 100 75 80 100 60 50 40 0 20 25 0 06452-017 50 fDATA = 50MSPS 60 60 Figure 21. AD9779A Third-Order IMD vs. fOUT, 8× Interpolation Figure 18. AD9779A Third-Order IMD vs.
AD9776A/AD9778A/AD9779A 95 90 EXT REF DC-COUPLED 0dBFS 85 –3dBFS 80 75 LGAV 51 W1 S2 S3 FC AA £(f): FTUN SWP –6dBFS 70 65 60 55 0 40 80 120 160 200 240 280 320 360 400 06452-117 50 fOUT (MHz) START 1.0MHz *RES BW 20kHz Figure 24. AD9779A IMD Performance vs. fOUT, Digital Full-Scale Input Over Output Frequency, 4× Interpolation, fDATA = 200 MSPS 06452-024 IMD (dBc) *ATTEN 20dB REF 0dBm *PEAK Log 10dB 100 STOP 400.0MHz SWEEP 1.203s (601 pts) VBW 20kHz Figure 27.
AD9776A/AD9778A/AD9779A –150 –55 –60 –154 –158 ACLR (dBc) NSD (dBm/Hz) –65 fDAC = 200MSPS fDAC = 400MSPS –162 fDAC = 800MSPS 0dBFS, PLL ENABLED –70 –6dBFS, PLL DISABLED –75 –80 –166 0 20 40 60 –90 100 80 06452-027 –170 fOUT (MHz) 0dBFS, PLL DISABLED –3dBFS, PLL DISABLED 0 20 40 60 80 100 120 140 160 180 200 220 240 260 06452-301 –85 fOUT (MHz) Figure 30. AD9779A Noise Spectral Density vs. fOUT, fDAC Over Output Frequency with a Single-Tone Input at −6 dBFS Figure 33.
AD9776A/AD9778A/AD9779A 100 1.5 90 fDATA = 200MSPS fDATA = 160MSPS 0.5 SFDR (dBc) 0 80 fDATA = 250MSPS 70 –0.5 60 –1.0 50 2k 0 4k 6k 8k 10k CODE 06452-033 –1.5 0 20 40 60 100 80 06452-036 INL (14-BIT LSB) 1.0 fOUT (MHz) Figure 36. AD9778A Typical INL Figure 39. AD9778A In-Band SFDR vs. fOUT, 2× Interpolation 0.6 0.4 –60 0 ACLR (dBc) DNL (14-BIT LSB) 0.2 –0.2 –70 FIRST ADJACENT CHANNEL THIRD ADJACENT CHANNEL –0.4 –80 –0.
AD9776A/AD9778A/AD9779A –150 0.20 0.15 –154 0.10 –158 DNL (12-BIT LSB) NSD (dBm/Hz) fDAC = 200MSPS fDAC = 400MSPS –162 fDAC = 800MSPS 0.05 0 –0.05 –0.10 –166 0 20 40 60 100 80 fOUT (MHz) –0.20 06452-039 –170 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 06452-042 –0.15 Figure 45. AD9776A Typical DNL Figure 42. AD9778A Noise Spectral Density vs.
AD9776A/AD9778A/AD9779A –55 –150 fDAC = 200MSPS –60 –154 fDAC = 400MSPS –65 –70 NSD (dBm/Hz) ACLR (dBc) FIRST ADJACENT CHANNEL THIRD ADJACENT CHANNEL –75 –80 SECOND ADJACENT CHANNEL –158 fDAC = 800MSPS –162 –166 25 50 75 100 125 150 175 200 225 –170 250 FOUT (MHz) 10 20 30 40 50 80 90 100 *ATTEN 4dB –150 fDAC = 200MSPS fDAC = 400MSPS NSD (dBm/Hz) –158 fDAC = 800MSPS –162 –166 PAVG 10 W1 S2 3.884MHz 3.840MHz 3.840MHz SPAN 50MHz SWEEP 162.
AD9776A/AD9778A/AD9779A TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. In-Band Spurious-Free Dynamic Range (SFDR) In-band SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate.
AD9776A/AD9778A/AD9779A THEORY OF OPERATION The AD9776A/AD9778A/AD9779A have many features that make them highly suited for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common quadrature modulators when designing single sideband transmitters. The speed and performance of the parts allow wider bandwidths and more carriers to be synthesized than in previously available DACs.
AD9776A/AD9778A/AD9779A 3-WIRE INTERFACE The 3-wire port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The port is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR protocols. The interface allows read and write access to all registers that configure the AD9776A/AD9778A/AD9779A.
AD9776A/AD9778A/AD9779A SERIAL INTERFACE PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and controls the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first format is active.
AD9776A/AD9778A/AD9779A 3-WIRE INTERFACE REGISTER MAP Note that all unused register bits should be kept at the device default values. Table 13. Register Name Comm Address Hex Decimal 0x00 00 Digital Control 0x01 01 0x02 02 Data format Single port 0x03 03 DATACLK delay mode 0x04 04 Reserved (set to 1) DATACLK Delay[3:0] 0x05 05 SYNC_O Delay[3:0] 0x06 0x07 06 07 PLL Control 0x08 0x09 08 09 Misc.
AD9776A/AD9778A/AD9779A Table 14.
AD9776A/AD9778A/AD9779A Register Name Sync Control Register Address 0x03 Bits 7 Parameter DATACLK delay mode 0x03 0x03 6 5:4 Reserved DATACLK Divide[1:0] 0x03 3:0 Data Timing Margin[3:0] 0x04 7:4 DATACLK Delay[3:0] 0x04 3:1 SYNC_O Divide[2:0] 0x04 0x05 0 7:4 SYNC_O Delay[4] SYNC_O Delay[3:0] 0x05 3:1 SYNC_I Ratio[2:0] 0x05 0x06 0 7:4 SYNC_I Delay[4] SYNC_I Delay[3:0] 0x06 0x07 0x07 0x07 3:0 7 6 5 SYNC_I Timing Margin[3:0] SYNC_I enable SYNC_O enable SYNC_O triggering edge 0x07 4
AD9776A/AD9778A/AD9779A Register Name PLL Control Misc.
AD9776A/AD9778A/AD9779A Register Name AUX DAC2 Control Interrupt Version Register Address 0x12 0x11 Bits 1:0 7:0 Parameter Auxiliary DAC2 Data[9:8] Auxiliary DAC2 Data[7:0] 0x12 7 Auxiliary DAC2 sign 0x12 6 0x12 5 Auxiliary DAC2 current direction Auxiliary DAC2 power-down Function Auxiliary DAC2 Data[9:0] is the 10-bit output current control word. Magnitude of the auxiliary DAC current increases with increasing value. Bit 9 is the MSB and Bit 0 is the LSB. 0: AUX2_P active. 1: AUX2_N active.
AD9776A/AD9778A/AD9779A INTERPOLATION FILTER ARCHITECTURE Table 15.
AD9776A/AD9778A/AD9779A 10 0 –10 –20 –20 –30 –40 –50 –60 –30 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 –4 –100 –4 –3 –2 –1 0 1 2 4 3 fOUT (× Input Data Rate) –3 –2 –1 0 1 2 3 4 fOUT (× Input Data Rate) Figure 58. 4× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off) 06452-058 ATTENUATION (dB) 0 –10 06452-055 ATTENUATION (dB) 10 Figure 61.
AD9776A/AD9778A/AD9779A 10 0 –10 –20 –20 –30 –40 –50 –60 –50 –60 –70 –80 –80 –90 –90 –100 –4 –100 –4 –3 –2 –1 0 1 2 3 4 –1 0 1 2 3 4 Shifted mode filter responses allow the pass band to be centered around ±0.5 fDATA, ±1.5 fDATA, ±2.5 fDATA, and ±3.5 fDATA. Switching to the shifted mode response does not affect the center frequency of the signal. Instead, the pass band of the filter is simply shifted.
AD9776A/AD9778A/AD9779A Table 19.
AD9776A/AD9778A/AD9779A 10 SHIFTED + 3 × fDAC /8 SHIFTED + fDAC/4 SHIFTED + fDAC/8 SHIFTED + DC SHIFTED – DC –40 –50 –80 –4 –3 –2 –30 –1 0 1 fOUT (× Input Data Rate), 2 ASSUMING 8× INTERPOLATION –40 3 4 06452-087 +fDAC /2 +fDAC /4 –70 Figure 70. Shifted Bandwidths Accessible with the Filter Architecture –50 –60 –70 –3 –2 –1 0 1 2 3 4 06452-065 –80 –4 fOUT (× Input Data Rate), ASSUMING 8× INTERPOLATION Figure 68.
AD9776A/AD9778A/AD9779A Table 20.
AD9776A/AD9778A/AD9779A SOURCING THE DAC SAMPLE CLOCK The AD9776A/AD9778A/AD9779A offer two modes of sourcing the DAC sample clock (DACCLK). The first mode employs an on-chip clock multiplier that accepts a reference clock operating at the lower input frequency, most commonly the data input frequency. The on-chip PLL then multiplies the reference clock up to a higher frequency, which can then be used to generate all of the internal clocks required by the DAC.
AD9776A/AD9778A/AD9779A Table 23. Typical VCO Frequency Range vs.
AD9776A/AD9778A/AD9779A Configuring PLL Band Select with Temperature Sensing Known Temperature Calibration with Memory The following procedure outlines a method for setting the PLL band select value for a device operating at a particular temperature that holds for a change in ambient temperature over the total −40°C to +85°C operating range of the device without further user intervention. Note that REFCLK must be applied to the device during this procedure.
AD9776A/AD9778A/AD9779A DRIVING THE REFCLK INPUT TTL OR CMOS CLK INPUT 0.1µF LVDS_P_IN REFCLK+ 50Ω 50Ω REFCLK+ REFCLK– 50Ω BAV99ZXCT HIGH SPEED DUAL DIODE 06452-069 The REFCLK input requires a low jitter differential drive signal. The signal level can range from 400 mV p-p differential to 1.6 V p-p differential centered about a 400 mV input commonmode voltage.
AD9776A/AD9778A/AD9779A FULL-SCALE CURRENT GENERATION INTERNAL REFERENCE AD9776A/AD9778A/AD9779A Internal current mirrors provide a current-gain scaling, where the I DAC or Q DAC gain is a 10-bit word in the 3-wire interface port register (Register 0x0B, Register 0x0C, Register 0x0F, and Register 0x10). The default value for the DAC gain registers gives an IFS of approximately 20 mA. IFS is equal to I DAC DAC FULL-SCALE REFERENCE CURRENT CURRENT SCALING I120 0.1µF 10kΩ 06452-073 1.
AD9776A/AD9778A/AD9779A GAIN AND OFFSET CORRECTION • Gain mismatch: The gain in the real and imaginary signal paths of the quadrature modulator may not be matched perfectly. This leads to less than optimal image rejection because the cancellation of the negative frequency image is less than perfect. • Local oscillator (LO) feedthrough: The quadrature modulator has a finite dc-referred offset, as well as coupling from its LO port to the signal inputs.
AD9776A/AD9778A/AD9779A RESULTS OF GAIN AND OFFSET CORRECTION 90 AUX1_P OUT1_N RBIP 50Ω RBIN 92 50Ω 250Ω AUX1_N 89 82pF C1I LPI 390nH 39pF C2I 21 IBBP RSLI 100Ω 22 82pF C3I The results of gain and offset correction can be seen in Figure 80 and Figure 81. Figure 80 shows the output spectrum of the quadrature demodulator before gain and offset correction. Figure 81 shows the output spectrum after correction. The LO feedthrough spur at 2.1 GHz has been suppressed to the noise level.
AD9776A/AD9778A/AD9779A INPUT DATA PORTS The AD9776A/AD9778A/AD9779A can operate in two data input modes: dual port mode and single port mode. For the default dual port mode (single port bit = 0), each DAC receives data from a dedicated input port. In single port mode (single port bit = 1), both DACs receive data from Port 1. In single port mode, DAC1 and DAC2 data is interleaved, and the TXENABLE input is used to steer data to the intended DAC.
AD9776A/AD9778A/AD9779A SYNC_I tH_SYNC tS_SYNC REFCLK tSREFCLK tHREFCLK Table 27. DACCLK to DATACLK Divisor Values ZS SP DATACLKDIV Value Interpolation factor (1, 2, 4, or 8) 1, if zero stuffing is disabled 2, if zero stuffing is enabled 0.
AD9776A/AD9778A/AD9779A The AD9776A/AD9778A/AD9779A have on-chip circuitry that enables the user to optimize the input data timing by adjusting the relationship between the DATACLK output and DCLK_SMP (the internal clock that samples the input data). This optimization is made by a sequence of 3-wire interface register read and write operations. The timing optimization can be done under strict control of the user, or the device can be programmed to maintain a configurable timing margin automatically.
AD9776A/AD9778A/AD9779A DEVICE SYNCHRONIZATION System demands can impose two different requirements for synchronization. Some systems require multiple DACs to be synchronized to each other. This is the case when supporting transmit diversity or beam forming, where multiple antennas are used to transmit a correlated signal. In this case, the DAC outputs need to be phase aligned with each other, but there may not be a requirement for the DAC outputs to be aligned with a system level reference clock.
AD9776A/AD9778A/AD9779A Figure 90 shows the timing of the SYNC_I input with respect to the REFCLK input. Note that although the timing is relative to the REFCLK signal, SYNC_I is sampled at the DACCLK rate. This means that the rising edge of the SYNC_I signal must occur after the hold time of the preceding DACCLK rising edge, not the preceding REFCLK rising edge.
AD9776A/AD9778A/AD9779A POWER DISSIPATION Figure 91 to Figure 99 show the power dissipation of the 1.8 V and 3.3 V digital and clock supplies in single DAC mode and dual DAC mode. In addition to this, the power dissipation/current of the 3.3 V analog supply (mode and speed independent) in single DAC mode is 102 mW/31 mA. In dual DAC mode, this is 182 mW/55 mA. When the PLL is enabled, it adds 50 mA/90 mW to the 1.8 V clock supply. 0.075 0.7 8× INTERPOLATION 0.
AD9776A/AD9778A/AD9779A 0.125 POWER-DOWN AND SLEEP MODES 8× INTERPOLATION, fDAC /8, fDAC /4, fDAC /2, NO MODULATION 0.100 4× INTERPOLATION POWER (W) 0.075 2× INTERPOLATION 0.050 0.025 1× INTERPOLATION, NO MODULATION 0 25 50 75 100 125 150 175 200 225 250 fDATA (MSPS) 06452-082 0 Figure 97. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC Mode, Does Not Include Zero Stuffing 0.
AD9776A/AD9778A/AD9779A EVALUATION BOARD OVERVIEW The typical evaluation setup is shown in Figure 100. A sine or square wave clock can be used to source the DAC sample clock. The spectral purity of the clock directly affects the device performance. A low noise, low jitter clock source is required. EVALUATION BOARD OPERATION The AD9776A/AD9778A/AD9779A evaluation board is provided to help users quickly become familiar with the operation of the device and to evaluate the device performance.
AD9776A/AD9778A/AD9779A The evaluation board comes with software that allows the user to program the on-chip configuration registers. Via the 3-wire interface port, the devices can be programmed into any of its various operating modes. The default software window is shown in Figure 102. The evaluation board also comes populated with the ADL537x modulator to allow for the evaluation of an RF subsystem.
AD9776A/AD9778A/AD9779A OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 1 SEATING PLANE 76 76 75 100 1 75 PIN 1 BOTTOM VIEW (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 50 25 50 1.05 1.00 0.95 7° 3.5° 0° 0.50 BSC 0.27 0.22 0.17 0.15 0.05 COPLANARITY 0.08 26 6.50 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
AD9776A/AD9778A/AD9779A NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06452-0-9/08(B) Rev.
