Datasheet

AD9777
Rev. C | Page 29 of 60
POWER DISSIPATION
The AD9777 has three voltage supplies: DVDD, AVDD, and
CLKVDD. Figure 49, Figure 50, and Figure 51 show the current
required from each of these supplies when each is set to the
3.3 V nominal specified for the AD9777. Power dissipation (P
D
)
can easily be extracted by multiplying the given curves by 3.3.
As Figure 49 shows, I
DVDD
is very dependent on the input data
rate, the interpolation rate, and the activation of the internal
digital modulator. I
DVDD
, however, is relatively insensitive to the
modulation rate by itself. In Figure 50, I
AVD D
shows the same
type of sensitivity to data, interpolation rate, and the modulator
function but to a much lesser degree (<10%). In Figure 51,
I
CLKVDD
varies over a wide range yet is responsible for only a
small percentage of the overall AD9777 supply current
requirement.
8× 4×
2×
1×
0
50
100
150
200
250
I
DVDD
(mA)
300
350
400
f
DATA
(MHz)
500 100 150 200
8×, (MOD. ON)
4×, (MOD. ON)
2×, (MOD. ON)
02706-049
Figure 49. I
DVDD
vs. f
DATA
vs. Interpolation Rate, PLL Disabled
8×, (MOD. ON)
8×
4×
2×
1×
72.0
72.5
73.0
73.5
74.0
74.5
I
AVDD
(mA)
75.0
75.5
76.0
f
DATA
(MHz)
500 100 150 200
4×, (MOD. ON)
2×, (MOD. ON)
02706-050
Figure 50. I
AVDD
vs. f
DATA
vs. Interpolation Rate, PLL Disabled
8×
4×
1×
2×
0
5
10
15
20
25
30
35
I
CLKVDD
(mA)
f
DATA
(MHz)
500 100 150 200
02706-051
Figure 51. I
CLKVDD
vs. f
DATA
vs. Interpolation Rate, PLL Disabled
SLEEP/POWER-DOWN MODES
(Control Register 00h, Bit 3 and Bit 4)
The AD9777 provides two methods for programmable
reduction in power savings. The sleep mode, when activated,
turns off the DAC output currents but the rest of the chip
remains functioning. When coming out of sleep mode, the
AD9777 immediately returns to full operation. Power-down
mode, on the other hand, turns off all analog and digital
circuitry in the AD9777 except for the SPI port. When
returning from power-down mode, enough clock cycles must
be allowed to flush the digital filters of random data acquired
during the power-down cycle. Note that optimal performance
with the PLL enabled is achieved with the UCO in the PLL
control loop running at 450 MHz to 550 MHz.
TWO PORT DATA INPUT MODE
The digital data input ports can be configured as two
independent ports or as a single (one-port mode) port. In the
two-port mode, data at the two input ports is latched into the
AD9777 on every rising edge of the data rate clock (DATACLK).
In addition, in the two-port mode, the AD9777 can be
programmed to generate an externally available DATACLK for
the purpose of data synchronization. This data rate clock can be
programmed to be available at either Pin 8 (DATACLK/
PLL_LOCK) or Pin 53 (SPI_SDO). Because Pin 8 can also
function as a PLL lock indicator when the PLL is enabled, there
are several options for configuring Pin 8 and Pin 53. The
following information describes these options.
PLL Off (Register 4, Bit 7 = 0)
Register 3, Bit 7 = 0; DATACLK out of Pin 8.
Register 3, Bit 7 = 1; DATACLK out of Pin 53.
PLL On (Register 4, Bit 7 = 1)
Register 3, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out
of Pin 8.