Datasheet

AD9777
Rev. C | Page 28 of 60
AD9777
INPUT
DATA
LATCHES
PLL_LOCK
1 = LOCK
0 = NO LOCK
SPI PORT
CLK+ CLK–
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
CLOCK
DISTRIBUTION
CIRCUITRY
INTERPOLATION
RATE
CONTROL
INTERNAL SPI
CONTROL
REGISTERS
MODULATION
RATE
CONTROL
PLL
CONTROL
(PLL ON)
PLL DIVIDER
(PRESCALER)
CONTROL
PRESCALER VCO
PHASE
DETECTOR
CHARGE
PUMP
2
1
48
02706-046
Figure 46. PLL and Clock Circuitry with PLL Disabled
In addition, if the zero stuffing option is enabled, the VCO doubles its
speed again. Phase noise can be slightly higher with the PLL enabled.
Figure 47 illustrates typical phase noise performance of the AD9777
with 2× interpolation and various input data rates. The signal
synthesized for the phase noise measurement was a single carrier at a
frequency of f
DATA
/4. The repetitive nature of this signal eliminates
quantization noise and distortion spurs as a factor in the measure-
ment. Although the curves blend in Figure 47, the different
conditions are given for clarity in the table preceding Figure 47.
Figure 47 also contains a table detailing PLL divider settings vs.
interpolation rate and maximum and minimum f
DATA
rates. Note that
maximum f
DATA
rates of 160 MSPS are due to the maximum input
data rate of the AD9777. However, maximum rates of less than 160
MSPS and all minimum f
DATA
rates are due to maximum and mini-
mum speeds of the internal PLL VCO. Figure 48 shows typical
performance of the PLL lock signal (Pin 8 or Pin 53) when the PLL is
in the process of locking.
Table 10. PLL Optimization
Interpolation
Rate
Divider
Setting
Minimum
f
DATA
Maximum
f
DATA
1 1 32 160
1 2 16 160
1 4 8 112
1 8 4 56
2 1 24 160
2 2 12 112
2 4 6 56
2 8 3 28
4 1 24 100
4 2 12 56
4 4 6 28
4 8 3 14
8 1 24 50
8 2 12 28
8 4 6 14
8 8 3 7
Table 11. Required PLL Prescaler Ration vs. f
DATA
f
DATA
(MSPS) PLL Prescaler Ratio
125 Disabled
125 Enabled Div 1
100 Enabled Div 2
75 Enabled Div 2
50 Enabled Div 4
–110
–100
–80
–40
–20
0
–60
–90
–50
–30
–10
–70
PHASE NOISE (dBFS)
012345
FREQUENCY OFFSET (MHz)
02706-047
Figure 47. Phase Noise Performance
02706-048
Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking
(Typical Lock Time)
It is important to note that the resistor/capacitor needed for the
PLL loop filter is internal on the AD9777. This suffices unless
the input data rate is below 10 MHz, in which case an external
series RC is required between the LPF and CLKVDD pins.