Datasheet

AD9777
Rev. C | Page 26 of 60
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
FINE REFERENCE CURRENT (mA)
0
1R MODE
2R MODE
FINE GAIN REGISTER CODE
(ASSUMING RSET1, RSET2 = 1.9k
Ω )
200 400 600 800 1000
02706-040
Figure 40. Fine Gain Effect on I
FULLSCALE
In Figure 42, the negative scale represents an offset added to
I
OUTB
, while the positive scale represents an offset added to I
OUTA
of the respective DAC. Offset Register 1 corresponds to IDAC,
while Offset Register 2 corresponds to QDAC. Figure 42
represents the AD9777 synthesizing a complex signal that is
then dc-coupled to an AD8345 quadrature modulator with an
LO of 800 MHz. The dc coupling allows the input offset of the
AD8345 to be calibrated out as well. The LO suppression at the
AD8345 output was optimized first by adjusting Offset
Register 1 in the AD9777. When an optimal point was found
(roughly Code 54), this code was held in Offset Register 1, and
Offset Register 2 was adjusted. The resulting LO suppression is
70 dBFS. These are typical numbers, and the specific code for
optimization varies from part to part.
0
1
2
3
4
5
OFFSET CURRENT (mA)
0
COARSE GAIN REGISTER CODE
(ASSUMING RSET1, RSET2 = 1.9k
Ω )
2R MODE
1R MODE
0 200 400 600 800 1000
02706-041
Figure 41. DAC Output Offset Current
–80
–70
–60
–50
–40
–30
LO SUPPRESSION (dBFS)
–20
–10
0
0–256–768 –512–1024 256 512 768 1024
DAC1, DAC2 (OFFSET REGISTER CODES)
OFFSET REGISTER 1 ADJUSTED
OFFSET REGISTER 2
ADJUSTED, WITH OFFSET
REGISTER 1 SET
TO OPTIMIZED VALUE
02706-042
Figure 42. Offset Adjust Control, Effect on LO Suppression
1R/2R MODE
In 2R mode, the reference current for each channel is set
independently by the FSADJ resistor on that channel. The
AD9777 can be programmed to derive its reference current
from a single resistor on Pin 60 by putting the part into 1R
mode. The transfer functions in Equation 1 are valid for 2R
mode. In 1R mode, the current developed in the single FSADJ
resistor is split equally between the two channels. The result is
that in 1R mode, a scale factor of 1/2 must be applied to the
formulas in Equation 1. The full-scale DAC current in 1R mode
can still be set to as high as 20 mA by using the internal 1.2 V
reference and a 950 Ω resistor instead of the 1.9 kΩ resistor
typically used in 2R mode.
CLOCK INPUT CONFIGURATION
The clock inputs to the AD9777 can be driven differentially or
single-ended. The internal clock circuitry has supply and
ground (CLKVDD, CLKGND) separate from the other supplies
on the chip to minimize jitter from internal noise sources.
Figure 43 shows the AD9777 driven from a single-ended clock
source. The CLK+/CLK− pins form a differential input
(CLKIN) so that the statically terminated input must be dc-
biased to the midswing voltage level of the clock driven input.
AD9777
R
SERIES
CLK+
CLK–
0.1µF
CLKVDD
CLKGND
V
THRESHOLD
02706-043
Figure 43. Single-Ended Clock Driving Clock Inputs