Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) TQFP 80 EP

16-Bit, 160 MSPS 2x/4x/8x

Interpolating Dual TxDAC+

D/A Converter

AD9777

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

FEATURES

16-bit resolution, 160 MSPS/400 MSPS input/output

data rate

Selectable 2×/4×/8× interpolating filter

Programmable channel gain and offset adjustment

/4, f

/8 digital quadrature modulation capability

Direct IF transmission mode for 70 MHz + IFs

Enables image rejection architecture

Fully compatible SPI® port

Excellent ac performance

SFDR −73 dBc @ 2 MHz to 35 MHz

WCDMA ACPR 71 dB @ IF = 19.2 MHz

Internal PLL clock multiplier

Selectable internal clock divider

Versatile clock input

Differential/single-ended sine wave or

TTL/CMOS/LVPECL compatible

Versatile input data interface

Twos complement/straight binary data coding

Dual-port or single-port interleaved input data

Single 3.3 V supply operation

Power dissipation: typical 1.2 W @ 3.3 V

On-chip 1.2 V reference

80-lead thin quad flat package, exposed pad (TQFP_EP)

APPLICATIONS

Communications

Analog quadrature modulation architecture

3G, multicarrier GSM, TDMA, CDMA systems

Broadband wireless, point-to-point microwave radios

Instrumentation/ATE

FUNCTIONAL BLOCK DIAGRAM

161616

/2 /2

AD9777

DATA

ASSEMBLER

LATCH

MUX

CONTROL

SPI INTERFACE AND

CONTROL REGISTERS

HALF-BAND FILTERS ALSO CAN BE

CONFIGURED FOR ZERO STUFFING ONLY

I AND Q

NONINTERLEAVED

OR INTERLEAVED

DATA

CLOCK OUT

WRITE

SELECT

HALF-

BAND

FILTER1*

FILTER

BYPASS

MUX

IMAGE

REJECTION/

DUAL DAC

MODE

BYPASS

MUX

I/Q DAC

GAIN/OFFSET

REGISTERS

HALF-

BAND

FILTER2*

HALF-

BAND

FILTER3*

COS

IDAC

VREF

IOFFSET

GAIN

DAC

DIFFERENTIAL

CLK

OFFSET

DAC

COS

OUT

PRESCALER

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

PHASE DETECTOR

AND VCO

SIN

DAC

/2, 4, 8

(

DAC

)

02706-001

Figure 1.

Summary of content (60 pages)

PAGE 1
6-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+® D/A Converter AD9777 FEATURES Versatile input data interface Twos complement/straight binary data coding Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: typical 1.2 W @ 3.3 V On-chip 1.
PAGE 2
AD9777 TABLE OF CONTENTS Features .............................................................................................. 1 Sleep/Power-Down Modes........................................................ 29 Applications....................................................................................... 1 Two Port Data Input Mode ....................................................... 29 General Description .........................................................................
PAGE 3
AD9777 REVISION HISTORY 1/06—Rev. B to Rev. C Updated Formatting .........................................................Universal Changes to Figure 32 .................................................................... 22 Changes to Figure 108 .................................................................. 54 Updated Outline Dimensions ..................................................... 58 Changes to Ordering Guide.........................................................
PAGE 4
AD9777 GENERAL DESCRIPTION The AD97771 is the 16-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system level options.
PAGE 5
AD9777 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 1.
PAGE 6
AD9777 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA, Interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) Output Settling Time (tST) (to 0.
PAGE 7
AD9777 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3.
PAGE 8
AD9777 DIGITAL FILTER SPECIFICATIONS 20 Table 4. Half-Band Filter No. 1 (43 Coefficients) 0 ATTENUATION (dBFS) –20 –40 –60 –80 –100 0.5 1.0 1.5 2.0 02706-003 0 2.0 02706-004 –120 8 02706-005 Coefficient 8 0 −29 0 67 0 −134 0 244 0 −414 0 673 0 −1,079 0 1,772 0 −3,280 0 10,364 16,384 fOUT (NORMALIZED TO INPUT DATA RATE) Figure 2.
PAGE 9
AD9777 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD AGND, DGND, CLKGND REFIO, FSADJ1/FSADJ2 IOUTA, IOUTB P1B15 to P1B0, P2B15 to P2B0, RESET DATACLK/PLL_LOCK CLK+, CLK− LPF SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect To AGND, DGND, CLKGND AVDD, DVDD, CLKVDD AGND, DGND, CLKGND AGND AGND DGND DGND CLKGND CLKGND DGND Min −0.3 −4.0 −0.3 −0.3 −1.0 −0.3 −0.3 −0.3 −0.3 −0.3 −65 Max +4.0 +4.0 +0.
PAGE 10
AD9777 AVDD AGND AVDD AGND AVDD AGND AGND IOUTB2 IOUTA2 AGND AGND IOUTB1 IOUTA1 AGND AGND AVDD AGND AVDD AGND AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 FSADJ1 59 FSADJ2 3 58 REFIO CLKGND 4 57 RESET CLK+ 5 56 SPI_CSB CLK– 6 55 SPI_CLK CLKGND 7 54 SPI_SDIO DATACLK/PLL_LOCK 8 53 SPI_SDO DGND 9 52 DGND 51 DVDD P1B15 (MSB) 11 50 P2B0 (LSB) P1B14 12 49 P2B1 P1B13 13 48 P2B2 P1B12
PAGE 11
AD9777 Table 8. Pin Function Description Pin No. 1, 3 2 4, 7 5 6 8 Mnemonic CLKVDD LPF CLKGND CLK+ CLK− DATACLK/PLL_LOCK 9, 17, 25, 35, 44, 52 10, 18, 26, 36, 43, 51 11 to 16, 19 to 24, 27 to 30 31 DGND Description Clock Supply Voltage. PLL Loop Filter. Clock Supply Common. Differential Clock Input. Differential Clock Input. With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock.
PAGE 12
AD9777 TERMINOLOGY Adjacent Channel Power Ratio (ACPR) A ratio in dBc between the measured power within a channel relative to its adjacent channel. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth.
PAGE 13
AD9777 TYPICAL PERFORMANCE CHARACTERISTICS 10 10 0 0 –10 –10 –20 –20 AMPLITUDE (dBm) –30 –40 –50 –60 –30 –40 –50 –60 –70 –70 –80 –80 –90 0 65 130 FREQUENCY (MHz) 02706-006 –90 0 50 100 02706-009 AMPLITUDE (dBm) T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, Interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. 150 FREQUENCY (MHz) Figure 6.
PAGE 14
AD9777 10 90 0dBFS 0 85 –10 –30 IMD (dBc) AMPLITUDE (dBm) 80 –20 –40 –50 –3dBFS 75 –6dBFS 70 65 –60 60 –70 55 –80 100 200 02706-012 0 300 FREQUENCY (MHz) 0 5 10 20 25 30 Figure 15. Third-Order IMD Products vs. Two-Tone fOUT @ fDATA = 65 MSPS Figure 12.
PAGE 15
AD9777 90 90 4× 0dBFS 85 85 80 80 –6dBFS 8× 1× 70 2× 65 75 70 65 60 60 55 55 50 10 20 30 40 50 60 FREQUENCY (MHz) 50 3.1 02706-018 0 3.3 3.4 3.5 AVDD (V) Figure 18. Third-Order IMD Products vs. Two-Tone fOUT and Interpolation Rate, 1× fDATA = 160 MSPS, 2× fDATA = 160 MSPS, 4× fDATA = 80 MSPS, 8× fDATA = 50 MSPS 90 3.2 02706-021 75 IMD (dBc) IMD (dBc) –3dBFS Figure 21. Third-Order IMD Products vs.
PAGE 16
AD9777 0 0 –10 –20 –30 AMPLITUDE (dBm) AMPLITUDE (dBm) –20 –40 –50 –60 –70 –40 –60 –80 –80 –90 50 100 150 FREQUENCY (MHz) 02706-024 0 0 5 10 15 20 25 30 35 40 45 FREQUENCY (MHz) 02706-027 –100 –100 Figure 27. Two-Tone IMD Performance, fDATA = 90 MSPS, Interpolation = 4× Figure 24.
PAGE 17
0 –10 –20 –20 –30 –30 AMPLITUDE (dBm) 0 –10 –40 –50 –60 –70 –40 –50 –60 –70 –80 –90 –90 –100 –100 0 100 200 300 400 FREQUENCY (MHz) Figure 30. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 50 MSPS, Interpolation = 8× 0 20 40 FREQUENCY (MHz) 60 80 02706-031 –80 02706-030 AMPLITUDE (dBm) AD9777 Figure 31. Eight-Tone IMD Performance, fDATA = 160 MSPS, Interpolation = 8x Rev.
PAGE 18
AD9777 MODE CONTROL (VIA SPI PORT) Table 9.
PAGE 19
AD9777 Address 0Ah Bit 7 Bit 6 Bit 5 Bit 4 0Bh QDAC Offset Adjustment Bit 9 QDAC Offset Adjustment Bit 8 QDAC Offset Adjustment Bit 7 QDAC Offset Adjustment Bit 6 0Ch QDAC IOFFSET Direction 0 = IOFFSET on IOUTA 1 = IOFFSET on IOUTB 0Dh 1 2 Bit 3 QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 5 Bit 2 QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 4 Bit 1 QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 3 QDAC Offset Adjustment Bit 1 Bit 0 QDAC Coarse Gain Adjustment QDAC
PAGE 20
AD9777 REGISTER DESCRIPTION Bit 3: Logic 1 enables zero stuffing mode for interpolation filters. Address 00h Bit 2: Default (1) enables the real mix mode. The I and Q data channels are individually modulated by fS/2, fS/4, or fS/8 after the interpolation filters. However, no complex modulation is done. In the complex mix mode (Logic 0), the digital modulators on the I and Q data channels are coupled to create a digital complex modulator.
PAGE 21
AD9777 Address 03h Address 05h, 09h Bit 7: This allows the data rate clock (divided down from the DAC clock) to be output at either the DATACLK/PLL_LOCK pin (Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this register enables the data rate clock at DATACLK/ PLL_LOCK, while a 1 in this register causes the data rate clock to be output at SPI_SDO. For more information, see the Two Port Data Input Mode section.
PAGE 22
AD9777 FUNCTIONAL DESCRIPTION The AD9777 dual interpolating DAC consists of two data channels that can be operated independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9777 capable of 2×, 4×, or 8× interpolation. High speed input and output data rates can be achieved within the following limitations.
PAGE 23
AD9777 INSTRUCTION BYTE SPI_CSB (Pin 56)—Chip Select The instruction byte contains the information shown below. Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SPI_SDO and SPI_SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle.
PAGE 24
AD9777 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO R/W I6(N) I5(N) I4 I3 I2 I1 I0 SDO D7N D6N D20 D10 D00 D7N D6N D20 D10 D00 02706-033 SCLK Figure 33. Serial Register Interface Timing MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CS I0 I1 I2 I3 I4 I5(N) I6(N) R/W SDO D00 D10 D20 D6N D7N D00 D10 D20 D6N D7N Figure 34.
PAGE 25
AD9777 The AD9777 serial port configuration bits reside in Bit 6 and Bit 7 of Register Address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle.
PAGE 26
AD9777 0 –10 –0.5 OFFSET REGISTER 1 ADJUSTED 1R MODE –1.0 2R MODE –1.5 –2.0 –20 –30 –40 –50 –60 –2.5 OFFSET REGISTER 2 ADJUSTED, WITH OFFSET REGISTER 1 SET TO OPTIMIZED VALUE –70 –3.0 200 400 600 800 –80 –1024 1000 02706-040 0 FINE GAIN REGISTER CODE (ASSUMING RSET1, RSET2 = 1.9kΩ) –512 –256 0 256 512 768 1024 DAC1, DAC2 (OFFSET REGISTER CODES) Figure 42. Offset Adjust Control, Effect on LO Suppression Figure 40.
PAGE 27
AD9777 AD9777 0.1µF 1kΩ CLK+ 1kΩ ECL/PECL 0.1µF 0.1µF CLKVDD 1kΩ CLK– CLKGND 02706-044 1kΩ Figure 44. Differential Clock Driving Clock Inputs A transformer, such as the T1-1T from Mini-Circuits, can also be used to convert a single-ended clock to differential. This method is used on the AD9777 evaluation board so that an external sine wave with no dc offset can be used as a differential clock.
PAGE 28
AD9777 CLK+ PLL_LOCK 1 = LOCK 0 = NO LOCK PHASE DETECTOR CHARGE PUMP 8 CLOCK DISTRIBUTION CIRCUITRY PRESCALER VCO –20 MODULATION RATE CONTROL PLL CONTROL (PLL ON) Figure 46. PLL and Clock Circuitry with PLL Disabled In addition, if the zero stuffing option is enabled, the VCO doubles its speed again. Phase noise can be slightly higher with the PLL enabled. Figure 47 illustrates typical phase noise performance of the AD9777 with 2× interpolation and various input data rates.
PAGE 29
AD9777 35 POWER DISSIPATION 8× 400 8×, (MOD. ON) IDVDD (mA) 300 8× 4× 2× 200 150 100 1× 50 50 100 150 200 fDATA (MHz) 02706-049 0 0 Figure 49. IDVDD vs. fDATA vs. Interpolation Rate, PLL Disabled 20 15 1× 10 5 0 50 100 150 200 fDATA (MHz) 02706-051 0 Figure 51. ICLKVDD vs. fDATA vs. Interpolation Rate, PLL Disabled The AD9777 provides two methods for programmable reduction in power savings.
PAGE 30
AD9777 tOD Register 3, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 53. Register 3, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8. Register 3, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53. Test configurations showing the various clocks that are required and generated by the AD9777 with the PLL enabled/disabled and in the one-port/two-port modes are given in Figure 101 to Figure 104.
PAGE 31
AD9777 The selection of the data for the I or Q channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9777 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 latches the data into the I channel on the clock rising edge, while IQSEL = 1 latches the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic 1).
PAGE 32
AD9777 tOD tOD CLKIN CLKIN DATACLK ONEPORTCLK DATA AT PORTS 1 AND 2 tH 02706-055 tS tOD = 6.5ns (MIN) TO 8.0ns (MAX) tS = 5.0ns (MAX) tH = –3.2ns (MAX) I AND Q INTERLEAVED INPUT DATA AT PORT 1 Figure 55. Timing Requirements in Two-Port Input Mode, with PLL Disabled tS tH PLL DISABLED, ONE-PORT MODE IQSEL tOD = 4.0ns (MIN) TO 5.5ns (MAX) tOD = 4.7ns (MAX) tS = 3.0ns (MAX) tH = –1.0ns (MAX) tIQS = 3.5ns (MAX) tIQH = –1.
PAGE 33
AD9777 e–jωt/2j The phase relationship of the modulated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, again with respect to the reference point of the viewer. Examples of sine and cosine modulation are given in Figure 58. SINE DC e–jωt/2j Ae–jωt/2j e–jωt/2 DC SINUSOIDAL MODULATION DC Figure 57.
PAGE 34
AD9777 MODULATION, NO INTERPOLATION With Control Register 01h, Bit 7 and Bit 6 set to 00, the interpolation function on the AD9777 is disabled. Figure 59 to Figure 62 show the DAC output spectral characteristics of the AD9777 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 01h, Bits 5 and 4. The tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth.
PAGE 35
AD9777 MODULATION, INTERPOLATION = 2× With Control Register 01h, Bit 7 and Bit 6 set to 01, the interpolation rate of the AD9777 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, −1). Figure 63 to Figure 66 represent the spectral response of the AD9777 DAC output with 2× interpolation in the various modulation modes to a narrow band baseband signal (again, the tall rectangles in the graphic).
PAGE 36
AD9777 MODULATION, INTERMODULATION = 4× With Control Register 01h, Bit 7 and Bit 6 set to 10, the interpolation rate of the AD9777 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, −1). Figure 67 to Figure 70 represent the spectral response of the AD9777 DAC output with 4× interpolation in the various modulation modes to a narrow band baseband signal.
PAGE 37
AD9777 MODULATION, INTERMODULATION = 8× With Control Register 01h, Bits 7 and 6, set to 11, the interpolation rate of the AD9777 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +0.707, +1, +0.707, 0, –0.707, −1, +0.707). Figure 71 to Figure 74 represent the spectral response of the AD9777 DAC output with 8× interpolation in the various modulation modes to a narrow band baseband signal.
PAGE 38
AD9777 ZERO STUFFING (Control Register 01h, Bit 3) As shown in Figure 75, a 0 or null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (fDAC). This is due to the inherent SIN(x)/x roll-off response in the digitalto-analog conversion. In applications where the desired frequency content is below fDAC/2, this may not be a problem. Note that at fDAC/2 the loss due to SIN(x)/x is 4 dB.
PAGE 39
AD9777 INPUT (REAL) OUTPUT (REAL) INPUT (IMAGINARY) OUTPUT INPUT (IMAGINARY) SINωt 90° 90° COSωt 02706-078 INPUT (REAL) Figure 78. Quadrature Modulation e–jωt = COSωt + jSINωt 02706-077 OUTPUT (IMAGINARY) Figure 77.
PAGE 40
AD9777 REAL CHANNEL (OUT) A/2 A/2 –FC1 FC –B/2J B/2J –FC FC REAL CHANNEL (IN) A DC COMPLEX MODULATOR TO QUADRATURE MODULATOR IMAGINARY CHANNEL (OUT) –A/2J A/2J –FC –FC B/2 B/2 –FC FC IMAGINARY CHANNEL (IN) B DC A/4 + B/4J A/4 – B/4J A/4 + B/4J A/4 – B/4J –FQ2 –FQ + FC –FQ – FC F Q – FC –A/4 – B/4J A/4 – B/4J A/4 + B/4J –A/4 + B/4J FQ FQ + FC OUT REAL QUADRATURE MODULATOR –FQ IMAGINARY FQ REJECTED IMAGES –FQ A/2 – B/2J FQ 1F = COMPLEX MODULATION FREQUENCY C 2F = QUADRATURE
PAGE 41
AD9777 COMPLEX BASEBAND SIGNAL A system in which multiple baseband signals are complex modulated and then applied to the AD9777 real and imaginary inputs, followed by a quadrature modulator, is shown in Figure 82, which also describes the transfer function of this system and the spectral output. Note the similarity of the transfer functions given in Figure 82 and Figure 80. Figure 82 adds an additional complex modulator stage for summing multiple carriers at the AD9777 inputs.
PAGE 42
AD9777 The complex carrier synthesized in the AD9777 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running at fDAC/2. As a result, complex modulation only functions with modulation rates of fDAC/4 and fDAC/8. Region A and Region B of Figure 83 to Figure 88 are the result of the complex signal described previously, when complex modulated in the AD9777 by +ejωt.
PAGE 43
AD9777 0 0 –20 –20 A B C D A B C –40 –40 –60 –60 –80 –80 D –1.5 –1.0 –0.5 0 0.5 1.0 1.5 –100 –2.0 2.0 –1.5 B –1.0 02706-083 –100 –2.0 A (LO) fOUT (×fDATA) –0.5 A 0 0.5 B 1.0 C 1.5 2.0 (LO) fOUT (×fDATA) Figure 83. 2× Interpolation, Complex fDAC/4 Modulation Figure 86. 2× Interpolation, Complex fDAC/8 Modulation 0 0 –20 –20 A B C D A B C –40 –40 –60 –60 –80 –80 D A –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 02706-084 –100 –4.
PAGE 44
0 0 –10 –10 –20 –20 –30 –30 AMPLITUDE (dBm) –40 –50 –60 –70 –40 –50 –60 –70 –80 –80 –90 –90 –100 10 20 30 40 02706-089 0 –100 750 50 FREQUENCY (MHz) 760 770 780 790 800 810 820 830 840 850 FREQUENCY (MHz) Figure 89. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 4×, No Modulation in AD9777 02706-092 AMPLITUDE (dBm) AD9777 Figure 92.
PAGE 45
AD9777 0 0 –10 –20 –30 AMPLITUDE (dBm) –40 –60 –40 –50 –60 –70 –80 –80 0 20 40 60 80 100 FREQUENCY (MHz) Figure 95. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 8×, Complex Modulation in AD9777 = +fDAC/8 –100 700 720 740 760 780 800 820 840 860 880 900 FREQUENCY (MHz) Figure 96. AD9777 Complex Output from Figure 95, Now Quadrature Modulated by AD8345 (LO = 800 MHz) Rev.
PAGE 46
AD9777 APPLYING THE OUTPUT CONFIGURATIONS A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage results if IOUTA and/or IOUTB is connected to a load resistor, RLOAD, referred to AGND. This configuration is most suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage.
PAGE 47
AD9777 DIFFERENTIAL COUPLING USING AN OP AMP Gain/Offset Adjust An op amp can also be used to perform a differential-to-single ended conversion, as shown in Figure 99. This has the added benefit of providing signal gain as well. In Figure 99, the AD9777 is configured with two equal load resistors, RLOAD, of 25 Ω. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration.
PAGE 48
AD9777 EVALUATION BOARD The AD9777 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from Windows® 95, Windows 98, or Windows NT®/2000. The evaluation board also contains an AD8345 quadrature modulator and support circuitry that allows the user to optimally configure the AD9777 in an image reject transmit signal chain.
PAGE 49
AD9777 LECROY TRIG PULSE INP GENERATOR SIGNAL GENERATOR DATACLK INPUT CLOCK AWG2021 OR DG2020 CLK+/CLK– 40-PIN RIBBON CABLE DAC1, DB15–DB0 DAC2, DB15–DB0 AD9777 JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON SOLDERED/IN × UNSOLDERED/OUT × × × × × × × × × × × × NOTES 1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED.
PAGE 50
AD9777 LECROY TRIG PULSE INP GENERATOR SIGNAL GENERATOR DATACLK INPUT CLOCK AWG2021 OR DG2020 CLK+/CLK– 40-PIN RIBBON CABLE DAC1, DB15–DB0 DAC2, DB15–DB0 AD9777 JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF SOLDERED/IN × UNSOLDERED/OUT × × × × × × × × × × × × NOTES 1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED.
PAGE 51
Figure 105. AD8345 Circuitry on AD9777 Evaluation Board O1P O1N 2 + C72 10V 10µF 02706-105 BCASE VDDM O2P C54 DNP CC0603 LC0805 CC0805 C78 0.1µF C75 0.
PAGE 52
Figure 106. AD9777 Clock, Power Supplies, and Output Circuitry 2 3 JP12 CX2 CX1 02706-106 JP3 IQ JP40 JP27 JP5 C29 0.1µF JP25 RC0603 R39 1kΩ JP32 R5 49.9Ω TP14 WHT DVDD; 14 DGND; 7 11 DVDD; 14 DGND; 7 RC0603 R1 200Ω DVDD DVDD DVDD DVDD c + C7 BCASE 10µF 6.3V + C8 10µF 6.3V BCASE + C9 10µF 6.3V BCASE + C10 10µF 6.3V C42 0.1µF CC0603 0.001µF CC0603 C23 0.001µF CC0603 C24 0.001µF CC0603 C25 0.001µF CC0603 C26 CLKN CLKP 0.1µF C11 CC0603 0.
PAGE 53
Rev.
PAGE 54
Rev.
PAGE 55
02706-109 AD9777 02706-110 Figure 109. AD9777 Evaluation Board Components, Top Side Figure 110. AD9777 Evaluation Board Components, Bottom Side Rev.
PAGE 56
02706-111 AD9777 02706-112 Figure 111. AD9777 Evaluation Board Layout, Layer One (Top) Figure 112. AD9777 Evaluation Board Layout, Layer Two (Ground Plane) Rev.
PAGE 57
02706-113 AD9777 02706-114 Figure 113. AD9777 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9777 Evaluation Board Layout, Layer Four (Bottom) Rev.
PAGE 58
AD9777 OUTLINE DIMENSIONS 14.20 14.00 SQ 13.80 0.75 0.60 0.45 1.20 MAX 12.20 12.00 SQ 11.80 80 61 61 1 60 80 1 60 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) BOTTOM VIEW 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 6.00 BSC SQ 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY (PINS UP) 20 41 40 21 VIEW A 41 20 21 40 0.50 BSC LEAD PITCH 0.27 0.22 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 115.
PAGE 59
AD9777 NOTES Rev.