4-Bit, 160 MSPS, 2×/4×/8× Interpolating Dual TxDAC+® Digital-to-Analog Converter AD9775 FEATURES Versatile input data interface Twos complement/straight binary data coding Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: 1.2 W @ 3.3 V typical On-chip, 1.
AD9775 TABLE OF CONTENTS Features .............................................................................................. 1 1R/2R Mode ................................................................................ 25 Applications....................................................................................... 1 Clock Input Configurations...................................................... 25 Functional Block Diagram ..............................................................
AD9775 REVISION HISTORY 12/06—Rev. D to Rev. E Changes to Figure 52, Figure 54, Figure 55, and Figure 56 .......29 1/06—Rev. C to Rev. D Updated Formatting..........................................................Universal Changes to Figure 32 .................................................................... 22 Changes to Figure 108 .................................................................. 55 Updated Outline Dimensions......................................................
AD9775 GENERAL DESCRIPTION The AD97751 is the 14-bit member of the AD977x pincompatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system-level options.
AD9775 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 1.
AD9775 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA, interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) Output Settling Time (tST) to 0.
AD9775 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3.
AD9775 DIGITAL FILTER SPECIFICATIONS 20 Table 4. Half-Band Filter No. 1 (43 Coefficients) 0 ATTENUATION (dBFS) –20 –40 –60 –80 –100 0.5 1.0 1.5 2.0 02858-002 0 2.0 02858-003 –120 8 02858-004 Coefficient 8 0 −29 0 67 0 −134 0 244 0 −414 0 673 0 −1079 0 1772 0 −3280 0 10,364 16,384 fOUT (NORMALIZED TO INPUT DATA RATE) Figure 2.
AD9775 ABSOLUTE MAXIMUM RATINGS Table 7.
AD9775 AVDD AGND AVDD AGND AVDD AGND AGND IOUTB2 IOUTA2 AGND AGND IOUTB1 IOUTA1 AGND AGND AVDD AGND AVDD AGND AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CLKVDD 1 60 FSADJ1 59 FSADJ2 CLKVDD 3 58 REFIO CLKGND 4 57 RESET CLK+ 5 56 SPI_CSB CLK– 6 55 SPI_CLK CLKGND 7 54 SPI_SDIO DATACLK/PLL_LOCK 8 53 SPI_SDO DGND 9 52 DGND 51 DVDD P1B13 (MSB) 11 50 NC P1B12 12 49 NC P1B11 13 48 P2B0 (
AD9775 Table 9. Pin Function Descriptions Pin No. 1, 3 2 4, 7 5 6 8 Mnemonic CLKVDD LPF CLKGND CLK+ CLK− DATACLK/PLL_LOCK Description Clock Supply Voltage. PLL Loop Filter. Clock Supply Common. Differential Clock Input. Differential Clock Input. With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock.
AD9775 TYPICAL PERFORMANCE CHARACTERISTICS 10 10 0 0 –10 –10 –20 –20 AMPLITUDE (dBm) –30 –40 –50 –60 –30 –40 –50 –60 –70 –70 –80 –80 –90 65 130 FREQUENCY (MHz) 02858-006 –90 0 0 50 100 02858-009 AMPLITUDE (dBm) T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. 150 FREQUENCY (MHz) Figure 6.
AD9775 10 90 –6dBFS 0 –3dBFS 85 –10 –30 IMD (dBc) AMPLITUDE (dBm) 80 –20 –40 –50 75 0dBFS 70 65 –60 60 –70 55 –80 –90 200 300 FREQUENCY (MHz) 0 5 10 15 20 25 30 FREQUENCY (MHz) Figure 12. Single-Tone Spectrum @ fDATA = 160 MSPS with fOUT = fDATA/3 02858-015 100 02858-012 50 0 Figure 15. Third-Order IMD Products vs.
AD9775 90 90 –3dBFS 85 85 80 80 4× 70 2× 1× 65 55 55 50 3.1 20 30 40 50 60 FREQUENCY (MHz) 02858-018 50 3.2 3.3 3.4 3.5 AVDD (V) Figure 18. Third-Order IMD Products vs. fOUT and Interpolation Rate, 1× fDATA = 160 MSPS, 2× fDATA = 160 MSPS, 4× fDATA = 80 MSPS, 8× fDATA = 50 MSPS Figure 21. Third-Order IMD Products vs.
0 0 –10 –10 –20 –20 –30 –30 AMPLITUDE (dBm) –40 –50 –60 –70 –40 –50 –60 –70 –80 –80 –90 –100 0 50 100 150 FREQUENCY (MHz) 02858-024 –90 –100 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) 02858-027 AMPLITUDE (dBm) AD9775 Figure 27. Two-Tone IMD Performance, fDATA = 150 MSPS, Interpolation = 4× Figure 24.
AD9775 0 0 –10 –20 AMPLITUDE (dBm) –30 –40 –50 –60 –70 –80 –40 –60 –80 –100 –90 0 100 200 300 400 FREQUENCY (MHz) 0 20 40 60 80 FREQUENCY (MHz) Figure 31. Eight-Tone IMD Performance, fDATA = 160 MSPS, Interpolation = 8× Figure 30. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 50 MSPS, Interpolation = 8× Rev.
AD9775 TERMINOLOGY Adjacent Channel Power Ratio (ACPR) A ratio in dBc between the measured power within a channel relative to its adjacent channel. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth.
AD9775 MODE CONTROL (VIA SPI PORT) Table 10.
AD9775 REGISTER DESCRIPTIONS ADDRESS 0x00 Bit 3: Logic 1 enables zero-stuffing mode for interpolation filters. Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an input during the data transfer (Phase 2) of the communications cycle. When set to 1, SPI_SDIO can act as an input or output, depending on Bit 7 of the instruction byte. Bit 2: Default (1) enables the real mix mode. The I and Q data channels are individually modulated by fS/2, fS/4, or fS/8 after the interpolation filters.
AD9775 ADDRESS 0x03 ADDRESS 0x05, ADDRESS 0x09 Bit 7: Allows the data rate clock (divided down from the DAC clock) to be output at either the DATACLK/PLL_LOCK pin (Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this register enables the data rate clock at DATACLK/ PLL_LOCK, while a 1 in this register causes the data rate clock to be output at SPI_SDO. For more information, see the Two-Port Data Input Mode section.
AD9775 FUNCTIONAL DESCRIPTION The AD9775 dual interpolating DAC consists of two data channels that can be operated independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9775 capable of 2×, 4×, or 8× interpolation. High speed input and output data rates can be achieved within the following limitations. SDO (PIN 53) SPI_CLK (PIN 55) CSB (PIN 56) Figure 32. SPI Port Interface Table 15.
AD9775 SPI_SDO (Pin 53)—Serial Data Out Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9775 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. INSTRUCTION BYTE The instruction byte contains the information shown next Table 16.
AD9775 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I6(N) R/W I5(N) I4 I3 I2 I1 I0 SDO D7N D6N D20 D10 D00 D7N D6N D20 D10 D00 02858-033 SCLK Figure 33. Serial Register Interface Timing MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CS I0 I1 I2 I3 I4 I5(N) I6(N) R/W SDO D00 D10 D20 D6N D7N D00 D10 D20 D6N D7N Figure 34.
AD9775 25 DAC OPERATION COARSE REFERENCE CURRENT (mA) The dual, 14-bit DAC output of the AD9775, along with the reference circuitry, gain, and offset registers, is shown in Figure 37. Note that an external reference can be used by simply overdriving the internal reference with the external reference. Referring to the transfer functions in Equation 1, a reference current is set by the internal 1.2 V reference, the external RSET resistor, and the values in the coarse gain register.
AD9775 –10 OFFSET REGISTER 1 ADJUSTED –20 –30 –40 –50 –60 OFFSET REGISTER 2 ADJUSTED, WITH OFFSET REGISTER 1 SET TO OPTIMIZED VALUE –70 –80 –1024 –768 –512 –256 256 512 768 CLOCK INPUT CONFIGURATIONS The clock inputs to the AD9775 can be driven differentially or single-ended. The internal clock circuitry has supply and ground (CLKVDD, CLKGND) separate from the other supplies on the chip to minimize jitter from internal noise sources.
AD9775 A transformer, such as the T1-1T from Mini-Circuits®, can also be used to convert a single-ended clock to differential. This method is used on the AD9775 evaluation board so that an external sine wave with no dc offset can be used as a differential clock. INTERPOLATION FILTERS, MODULATORS, AND DACS 2 The charge pump, VCO, differential clock input buffer, phase detector, prescaler, and clock distribution are all powered from CLKVDD.
AD9775 In addition, if the zero-stuffing option is enabled, the VCO doubles its speed again. Phase noise may be slightly higher with the PLL enabled. Figure 47 illustrates typical phase noise performance of the AD9775 with 2× interpolation and various input data rates. The signal synthesized for the phase noise measurement was a single carrier at a frequency of fDATA/4. The repetitive nature of this signal eliminates quantization noise and distortion spurs as a factor in the measurement.
AD9775 35 PLL On (Register 4, Bit 7 = 1) 8× Register 3, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 8. Register 3, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 53. Register 3, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8. Register 3, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53. 30 4× 2× ICLKVDD (mA) 25 20 15 1× 10 5 0 50 100 150 02858-051 0 200 fDATA (MHz) Figure 51 ICLKVDD vs. fDATA vs.
AD9775 DATACLK INVERSION PLL ENABLED, ONE-PORT MODE (Control Register 0x02, Bit 4) (Control Register 0x02, Bit 6 to Bit 1 and Control Register 0x04, Bit 7 to Bit 1) By programming this bit, the DATACLK signal shown in Figure 52 can be inverted. With inversion enabled, tOD refers to the time between the rising edge of CLKIN and the falling edge of DATACLK. No other effect on timing occurs. tOD CLKIN DATACLK DATA AT PORTS 1 AND 2 tH 02858-052 tS tOD = 1.5ns (MIN) TO 2.5ns (MAX) tS = 0.
AD9775 tOD ONEPORTCLK DRIVER STRENGTH The drive capability of ONEPORTCLK is identical to that of DATACLK in the two-port mode. Refer to Figure 53 for performance under load conditions. CLKIN IQ PAIRING (Control Register 0x02, Bit 0) DATACLK DATA AT PORTS 1 AND 2 tS Given the following interleaved data stream, where the data indicates the value with respect to full scale: tOD = 6.5ns (MIN) TO 8.0ns (MAX) tS = 5.0ns (MIN) tH = –3.
AD9775 frequency images. This is shown graphically in the frequency domain in Figure 57. e–jωt/2j SINE DC One-port mode is very useful when interfacing with devices such as the Analog Devices AD6622 or AD6623 transmit signal processors, in which two digital data channels have been interleaved (multiplexed).
AD9775 MODULATION, NO INTERPOLATION With Control Register 0x01, Bit 7 and Bit 6 set to 00, the interpolation function on the AD9775 is disabled. Figure 59 through Figure 62 show the DAC output spectral characteristics of the AD9775 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 0x01, Bit 5 and Bit 4. The tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth.
AD9775 MODULATION, INTERPOLATION = 2× With Control Register 0x01, Bit 7 and Bit 6 set to 01, the interpolation rate of the AD9775 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, −1). Figure 63 through Figure 66 represent the spectral response of the AD9775 DAC output with 2× interpolation in the various modulation modes to a narrowband baseband signal (the tall rectangles in the graphic).
AD9775 MODULATION, INTERPOLATION = 4× With Control Register 0x01, Bit 7 and Bit 6 set to 10, the interpolation rate of the AD9775 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, −1). Figure 67 through Figure 70 represent the spectral response of the AD9775 DAC output with 4× interpolation in the various modulation modes to a narrow-band baseband signal.
AD9775 MODULATION, INTERPOLATION = 8× With Control Register 0x01, Bit 7 and Bit 6 set to 11, the interpolation rate of the AD9775 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +0.707, +1, +0.707, 0, −0.707, −1, +0.707). Figure 71 through Figure 74 represent the spectral response of the AD9775 DAC output with 8× interpolation in the various modulation modes to a narrow-band baseband signal.
AD9775 ZERO STUFFING (Control Register 0x01, Bit 3) As shown in Figure 75, a 0 or null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (fDAC). This is due to the inherent sin(x)/x roll-off response in the digital-toanalog conversion. In applications where the desired frequency content is below fDAC/2, this may not be a problem. Note that at fDAC/2 the loss due to sin(x)/x is 4 dB.
AD9775 the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit frequency. It is important to remember that in this application (two baseband data channels) the image rejection is not dependent on the data at either of the AD9775 input channels. In fact, image rejection still occurs with either one or both of the AD9775 input channels active.
AD9775 data on any channel. Image rejection on a channel occurs if either the real or imaginary data, or both, is present on the baseband channel. IMAGE REJECTION AND SIDEBAND SUPPRESSION OF MODULATED CARRIERS As shown in Figure 79, image rejection can be achieved by applying baseband data to the AD9775 and following the AD9775 with a quadrature modulator. To process multiple carriers while still maintaining image reject capability, each carrier must be complex modulated.
AD9775 The complex carrier synthesized in the AD9775 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running at fDAC/2. As a result, complex modulation only functions with modulation rates of fDAC/4 and fDAC/8. Regions A and B of Figure 83 to Figure 88 are the result of the complex signal described previously, when complex modulated in the AD9775 by +ejωt.
AD9775 0 –20 –20 D A B C D A B DA C –40 –40 –60 –60 –80 –80 –6.0 –4.0 –2.0 0 2.0 4.0 6.0 –100 –8.0 8.0 –6.0 –4.0 –2.0 02858-085 –100 –8.0 BC (LO) fOUT (×fDATA) DA BC 0 2.0 4.0 6.0 8.0 02858-088 0 (LO) fOUT (×fDATA) Figure 85. 8× Interpolation, Complex fDAC/4 Modulation Figure 88. 8× Interpolation, Complex fDAC/8 Modulation 0 0 –10 –20 –20 AMPLITUDE (dBm) –40 D A B CD A B –30 C –60 –40 –50 –60 –70 –80 –80 –90 –1.0 –0.5 0 0.5 1.0 1.5 –100 2.
0 0 –10 –10 –20 –20 –30 –30 AMPLITUDE (dBm) –40 –50 –60 –70 –40 –50 –60 –70 –80 –80 –100 750 10 20 30 40 50 FREQUENCY (MHz) 02858-091 0 780 790 800 810 820 830 840 850 Figure 94.
AD9775 APPLYING THE OUTPUT CONFIGURATIONS A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage results if IOUTA and/or IOUTB is connected to a load resistor, RLOAD, referred to AGND. This configuration is most suitable for a single-supply system requiring a dc-coupled, ground-referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage.
AD9775 DIFFERENTIAL COUPLING USING AN OP AMP Gain/Offset Adjust An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 99. This has the added benefit of providing signal gain as well. In Figure 99, the AD9775 is configured with two equal load resistors, RLOAD, of 25 Ω. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration.
AD9775 EVALUATION BOARD The AD9775 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from PCs running Windows® 95, Windows 98, or Windows NT®/2000. The evaluation board also contains an AD8345 quadrature modulator and support circuitry that allows the user to optimally configure the AD9775 in an image reject transmit signal chain.
AD9775 LECROY TRIG PULSE INP GENERATOR SIGNAL GENERATOR DATACLK INPUT CLOCK AWG2021 OR DG2020 CLK+/CLK– 40-PIN RIBBON CABLE DAC1, DB13–DB0 DAC2, DB13–DB0 AD9775 JUMPER CONFIGURATION FOR TWO-PORT MODE PLL ON SOLDERED/IN × UNSOLDERED/OUT × × × × × × × × × × × × NOTES 1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED.
AD9775 LECROY TRIG PULSE INP GENERATOR SIGNAL GENERATOR DATACLK INPUT CLOCK AWG2021 OR DG2020 CLK+/CLK– 40-PIN RIBBON CABLE DAC1, DB13–DB0 DAC2, DB13–DB0 AD9775 JUMPER CONFIGURATION FOR TWO-PORT MODE PLL OFF SOLDERED/IN × UNSOLDERED/OUT × × × × × × × × × × × × NOTES 1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED.
Figure 105. AD8345 Circuitry on AD9775 Evaluation Board O1P O1N 2 + C72 10V 10μF 02858-105 BCASE VDDM O2P C54 DNP CC0603 LC0805 CC0805 C78 0.1μF C75 0.
Figure 106. AD9775 Clock, Power Supplies, and Output Circuitry 2 3 JP12 CX2 CX1 02858-106 JP3 IQ JP40 JP27 JP5 C29 0.1μF JP25 RC0603 R39 1kΩ JP32 R5 49.9Ω TP14 WHT DVDD; 14 DGND; 7 11 DVDD; 14 DGND; 7 RC0603 R1 200Ω DVDD DVDD DVDD DVDD c + C7 BCASE 10μF 6.3V + C8 10μF 6.3V BCASE + C9 10μF 6.3V BCASE + C10 10μF 6.3V C42 0.1μF CC0603 0.001μF CC0603 C23 0.001μF CC0603 C24 0.001μF CC0603 C25 0.001μF CC0603 C26 CLKN CLKP 0.1μF C11 CC0603 0.
Rev.
Rev.
02858-109 AD9775 02858-110 Figure 109. AD9775 Evaluation Board Components, Top Side Figure 110. AD9775 Evaluation Board Components, Bottom Side Rev.
02858-111 AD9775 02858-112 Figure 111. AD9775 Evaluation Board Layout, Layer One (Top) Figure 112. AD9775 Evaluation Board Layout, Layer Two (Ground Plane) Rev.
02858-113 AD9775 02858-114 Figure 113. AD9775 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9775 Evaluation Board Layout, Layer Four (Bottom) Rev.
AD9775 OUTLINE DIMENSIONS 14.20 14.00 SQ 13.80 0.75 0.60 0.45 1.20 MAX 12.20 12.00 SQ 11.80 80 61 61 1 60 80 1 60 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) BOTTOM VIEW 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 6.00 BSC SQ 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY (PINS UP) 20 41 40 21 VIEW A 41 20 21 40 0.50 BSC LEAD PITCH 0.27 0.22 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 115.
AD9775 NOTES Rev.
AD9775 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02858-0-12/06(E) Rev.
