Datasheet

AD9773
Rev. D | Page 32 of 60
ONEPORTCLK DRIVER STRENGTH
The drive capability of ONEPORTCLK is identical to that of
DATACLK in the two-port mode. Refer to
Figure 53 for
performance under load conditions.
t
OD
t
S
t
IQS
t
IQH
t
OD
= 4.0ns (MIN)
TO 5.5ns (MAX)
t
S
= 3.0ns (MAX)
t
H
= –0.5ns (MAX)
t
IQS
= 3.5ns (MAX)
t
IQH
= –1.5ns (MAX)
t
H
CLKIN
ONEPORTCLK
IQSEL
I AND Q INTERLEAVED
INPUT DATA AT PORT 1
02857-054
Figure 54. Timing Requirements in One-Port
Input Mode with the PLL Enabled
IQ PAIRING
(Control Register 02h, Bit 0)
In one-port mode, the interleaved data is latched into the
AD9773 internal I and Q channels in pairs. The order of how
the pairs are latched internally is defined by this control register.
The following is an example of the effect this has on incoming
interleaved data.
Given the following interleaved data stream, where the data
indicates the value with respect to full scale:
I Q I Q I Q I Q I Q
0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5
With the control register set to 0 (I first), the data appears at the
internal channel inputs in the following order in time:
I Channel 0.5 1 0.5 0 0.5
Q Channel 0.5 1 0.5 0 0.5
With the control register set to 1 (Q first), the data appears at
the internal channel inputs in the following order in time:
I Channel 0.5 1 0.5 0 0.5 x
Q Channel y 0.5 1 0.5 0 0.5
The values x and y represent the next I value and the previous
Q value in the series.
PLL DISABLED, TWO-PORT MODE
With the PLL disabled, a clock at the DAC output rate must be
applied to CLKIN. Internal clock dividers in the AD9773
synthesize the DATACLK signal at Pin 8, which runs at the
input data rate and can be used to synchronize the input data.
Data is latched into input Ports 1 and 2 of the AD9773 on the
rising edge of DATACLK. DATACLK speed is defined as the
speed of CLKIN divided by the interpolation rate. With zero
stuffing enabled, this division increases by a factor of 2.
Figure 55
illustrates the delay between the rising edge of CLKIN and the
rising edge of DATACLK, as well as t
S
and t
H
in this mode.
The programmable modes DATACLK inversion and DATACLK
driver strength described in the previous section (
PLL Enabled,
Two-Port Mode
) have identical functionality with the PLL
disabled.
The data rate clock created by dividing down the DAC clock in
this mode can be programmed (via Register 03h, Bit 7) to be
output from the SPI_SDO pin, rather than the DATACLK pin.
In some applications, this may improve complex image
rejection. When SPI_SDO is used as data rate clock out, t
OD
increases by 1.6 ns.
t
OD
t
S
t
H
t
OD
= 6.5ns (MIN) TO 8.0ns (MAX)
t
S
= 5.0ns (MAX)
t
H
= –3.2ns (MAX)
CLKIN
DATACLK
DATA AT PORT
S
1 AND 2
02857-055
Figure 55. Timing Requirements in Two-Port
Input Mode with PLL Disabled
PLL DISABLED, ONE-PORT MODE
In one-port mode, data is received into the AD9773 as an
interleaved stream on Port 1. A clock signal (ONEPORTCLK),
running at the interleaved data rate, which is 2× the input data
rate of the internal I and Q channels, is available for data
synchronization at Pin 32.
With PLL disabled, a clock at the DAC output rate must be
applied to CLKIN. Internal dividers synthesize the ONEPORTCLK
signal at Pin 32. The selection of the data for the I or Q channel
is determined by the state of the logic level applied to Pin 31
(IQSEL when the AD9773 is in one-port mode) on the rising
edge of ONEPORTCLK.