Datasheet

AD9773
Rev. D | Page 29 of 60
02857-048
Figure 48. PLL_LOCK Output Signal (Pin 8) in the
Process of Locking (Typical Lock Time)
It is important to note that the resistor/capacitor needed for the
PLL loop filter is internal on the AD9773. This suffices unless the
input data rate is below 10 MHz, in which case an external series
RC is required between the LPF and CLKVDD pins.
POWER DISSIPATION
The AD9773 has three voltage supplies: DVDD, AVDD, and
CLKVDD.
Figure 49, Figure 50, and Figure 51 show the current
required from each of these supplies when each is set to the
3.3 V nominal specified for the AD9773. Power dissipation (P
D
)
can easily be extracted by multiplying the given curves by 3.3.
As
Figure 49 shows, I
DVDD
is very dependent on the input data
rate, the interpolation rate, and the activation of the internal
digital modulator. I
DVDD
, however, is relatively insensitive to the
modulation rate by itself. In
Figure 50, I
AVD D
shows the same
type of sensitivity to the data, the interpolation rate, and the
modulator function but to a much lesser degree (<10%). In
Figure 51, I
CLKVDD
varies over a wide range yet is responsible for
only a small percentage of the overall AD9773 supply current
requirements.
8× 4×
2×
1×
0
50
100
150
200
250
I
DVDD
(mA)
300
350
400
f
DATA
(MHz)
500 100 150 200
8×, (MOD. ON)
4×, (MOD. ON)
2×, (MOD. ON)
02857-049
Figure 49. I
DVDD
vs. f
DATA
vs. Interpolation Rate, PLL Disabled
8×, (MOD. ON)
8×
4×
2×
1×
72.0
72.5
73.0
73.5
74.0
74.5
I
AVDD
(mA)
75.0
75.5
76.0
f
DATA
(MHz)
500 100 150 200
4×, (MOD. ON)
2×, (MOD. ON)
02857-050
Figure 50. I
AVDD
vs. f
DATA
vs. Interpolation Rate, PLL Disabled
8 ×
4 ×
1 ×
2 ×
0
5
10
15
20
25
30
35
I
CLKVDD
(mA)
f
DATA
(MHz)
500 100 150 200
02857-051
Figure 51. I
CLKVDD
vs. f
DATA
vs. Interpolation Rate, PLL Disabled
SLEEP/POWER-DOWN MODES
(Control Register 00h, Bit 3 and Bit 4)
The AD9773 provides two methods for programmable
reduction in power savings. The sleep mode, when activated,
turns off the DAC output currents but the rest of the chip
remains functioning. When coming out of sleep mode, the
AD9773 immediately returns to full operation. Power-down
mode, on the other hand, turns off all analog and digital
circuitry in the AD9773 except for the SPI port. When
returning from power-down mode, enough clock cycles must
be allowed to flush the digital filters of random data acquired
during the power-down cycle.