Datasheet

AD9773
Rev. D | Page 28 of 60
AD9773
PLLVDD
INPUT
DATA
LATCHES
PLL_LOCK
1 = LOCK
0 = NO LOCK
SPI PORT
LPF
CLK+ CLK–
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
CLOCK
DISTRIBUTION
CIRCUITRY
INTERPOLATION
RATE
CONTROL
INTERNAL SPI
CONTROL
REGISTERS
MODULATION
RATE
CONTROL
PLL
CONTROL
(PLL ON)
PLL DIVIDER
(PRESCALER)
CONTROL
PRESCALER VCO
PHASE
DETECTOR
CHARGE
PUMP
2
1
48
02857-045
Figure 45. PLL and Clock Circuitry with PLL Enabled
AD9773
INPUT
DATA
LATCHES
PLL_LOCK
1 = LOCK
0 = NO LOCK
SPI PORT
CLK+ CLK–
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
CLOCK
DISTRIBUTION
CIRCUITRY
INTERPOLATION
RATE
CONTROL
INTERNAL SPI
CONTROL
REGISTERS
MODULATION
RATE
CONTROL
PLL
CONTROL
(PLL ON)
PLL DIVIDER
(PRESCALER)
CONTROL
PRESCALER VCO
PHASE
DETECTOR
CHARGE
PUMP
2
1
48
02857-046
Figure 46. PLL and Clock Circuitry with PLL Disabled
In addition, if the zero stuffing option is enabled, the VCO
doubles its speed again. Phase noise may be slightly higher with
the PLL enabled.
Figure 47 illustrates typical phase noise
performance of the AD9773 with 2× interpolation and various
input data rates. The signal synthesized for the phase noise
measurement was a single carrier at a frequency of f
DATA
/4. The
repetitive nature of this signal eliminates quantization noise and
distortion spurs as a factor in the measurement. Although the
curves blend together in
Figure 47, the different conditions are
given for clarity in
Tabl e 17. Table 16 details PLL divider
settings vs. interpolation rate and maximum and minimum
f
DATA
rates. Note that the maximum f
DATA
rates of 160 MSPS are
due to the maximum input data rate of the AD9773.
However, maximum rates of less than 160 MSPS and all
minimum f
DATA
rates are due to the maximum and minimum
speeds of the internal PLL VCO.
Figure 48 shows typical
performance of the PLL lock signal (Pin 8 or Pin 53) when the
PLL is in the process of locking.
Table 16. PLL Optimization
Interpolation
Rate
Divider
Setting
Minimum
f
DATA
Maximum
f
DATA
1 1 32 160
1 2 16 160
1 4 8 112
1 8 4 56
2 1 24 160
2 2 12 112
2 4 6 56
2 8 3 28
4 1 24 100
4 2 12 56
4 4 6 28
4 8 3 14
8 1 24 50
8 2 12 28
8 4 6 14
8 8 3 7
Table 17. Required PLL Prescaler Ratio vs. f
DATA
f
DATA
PLL Prescaler Ratio
125 MSPS Disabled
125 MSPS Enabled Div 1
100 MSPS Enabled Div 2
75 MSPS Enabled Div 2
50 MSPS Enabled Div 4
–110
–100
–80
–40
–20
0
–60
–90
–50
–30
–10
–70
PHASE NOISE (dBFS)
012345
FREQUENCY OFFSET (MHz)
02857-047
Figure 47. Phase Noise Performance