Datasheet

AD9773
Rev. D | Page 24 of 60
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CS
S
CL
K
SDIO
SDO
R/W I4 I3 I2 I1 I0 D7
N
D6
N
D7
N
D6
N
D2
0
D1
0
D0
0
D2
0
D1
0
D0
0
I6
(N)
I5
(N)
02857-033
Figure 33. Serial Register Interface Timing MSB First
CS
SCLK
SDIO
SDO
INSTRUCTION CYCLE DATA TRANSFER CYCLE
I0 I1 I2 I3 I4 I5
(N)
I6
(N)
R/W D0
0
D1
0
D2
0
D6
N
D7
N
D0
0
D1
0
D2
0
D6
N
D7
N
02857-034
Figure 34. Serial Register Interface Timing LSB First
T
CS
SCLK
SDIO
t
DS
t
SCLK
t
PWH
t
DS
t
DH
t
PWL
INSTRUCTION BIT 7 INSTRUCTION BIT 6
02857-035
Figure 35. Timing Diagram for Register Write to AD9773
CS
SCLK
SDIO
SDO
DATA BIT N
t
DV
DATA BIT N–1
02857-036
Figure 36. Timing Diagram for Register Read from AD9773