2-Bit, 160 MSPS, 2×/4×/8× Interpolating Dual TxDAC D/A Converter AD9773 FEATURES Versatile input data interface Twos complement/straight binary data coding Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: typical 1.2 W @ 3.3 V On-chip 1.
AD9773 TABLE OF CONTENTS Features .............................................................................................. 1 Two-Port Data Input Mode ...................................................... 30 Applications....................................................................................... 1 One-/Two-Port Input Modes.................................................... 30 Functional Block Diagram ..........................................................
AD9773 1/06—Rev. B to Rev. C Updated Formatting .........................................................Universal Changes to Figure 32 .................................................................... 22 Changes to Figure 108 .................................................................. 55 Updated Outline Dimensions ..................................................... 58 Changes to Ordering Guide......................................................... 58 4/04—Data Sheet Changed from Rev.
AD9773 GENERAL DESCRIPTION The AD9773 1 is the 12-bit member of the AD977x pincompatible, high performance, programmable 2×/4×/8× interpolating TxDAC+® family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system-level options.
AD9773 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 1.
AD9773 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA, interpolation = 2×, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) Output Settling Time (tST) (to 0.
AD9773 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3.
AD9773 DIGITAL FILTER SPECIFICATIONS 20 Table 4. Half-Band Filter No. 1 (43 Coefficients) 0 ATTENUATION (dBFS) –20 –40 –60 –80 –100 0.5 1.0 1.5 2.0 02857-002 0 2.0 02857-003 –120 8 02857-004 Coefficient 8 0 −29 0 67 0 −134 0 244 0 −414 0 673 0 −1079 0 1772 0 −3280 0 10,364 16,384 fOUT (NORMALIZED TO INPUT DATA RATE) Figure 2.
AD9773 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD AGND, DGND, CLKGND REFIO, FSADJ1/FSADJ2 IOUTA, IOUTB P1B11 to P1B0, P2B11 to P2B0, RESET DATACLK, PLL_LOCK CLK+, CLK− LPF SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect To AGND, DGND, CLKGND AVDD, DVDD, CLKVDD AGND, DGND, CLKGND AGND AGND DGND DGND CLKGND CLKGND DGND Min −0.3 −4.0 −0.3 −0.3 −1.0 −0.3 −0.3 −0.3 −0.3 −0.
AD9773 AVDD AGND AVDD AGND AVDD AGND AGND IOUTB2 IOUTA2 AGND AGND IOUTB1 IOUTA1 AGND AGND AVDD AGND AVDD AGND AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CLKVDD 1 LPF 2 CLKVDD 60 FSADJ1 59 FSADJ2 3 58 REFIO CLKGND 4 57 RESET CLK+ 5 56 SPI_CSB CLK– 6 55 SPI_CLK CLKGND 7 54 SPI_SDIO DATACLK/PLL_LOCK 8 53 SPI_SDO DGND 9 52 DGND 51 DVDD P1B11 (MSB) 11 50 NC P1B10 12 49 NC P1B9 13
AD9773 Table 8. Pin Function Descriptions Pin No. 1, 3 2 4, 7 5 6 8 Mnemonic CLKVDD LPF CLKGND CLK+ CLK− DATACLK/PLL_LOCK 9, 17, 25, 35, 44, 52 10, 18, 26, 36, 43, 51 11 to 16, 19 to 24, 27 to 30, 47 to 50 31 DGND Description Clock Supply Voltage. PLL Loop Filter. Clock Supply Common. Differential Clock Input. Differential Clock Input. With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state.
AD9773 TYPICAL PERFORMANCE CHARACTERISTICS 10 10 0 0 –10 –10 –20 –20 AMPLITUDE (dBm) –30 –40 –50 –60 –30 –40 –50 –60 –70 –70 –80 –80 –90 130 FREQUENCY (MHz) 0 50 100 150 FREQUENCY (MHz) Figure 6. Single-Tone Spectrum @ fDATA = 65 MSPS with fOUT = fDATA/3 Figure 9.
AD9773 90 10 –6dBFS –3dBFS 0 85 –10 –30 IMD (dBc) AMPLITUDE (dBm) 80 –20 –40 –50 75 0dBFS 70 65 –60 60 –70 55 –80 100 200 02857-012 0 300 FREQUENCY (MHz) 0 10 20 30 FREQUENCY (MHz) 02857-015 50 –90 Figure 15. Third-Order IMD Products vs. fOUT @ fDATA = 65 MSPS Figure 12.
AD9773 90 90 –3dBFS 8× –6dBFS 85 85 4× 80 80 75 75 1× 70 2× 65 70 65 60 60 55 55 50 3.1 0 20 40 02857-018 50 60 FREQUENCY (MHz) 4× 3.3 3.4 3.5 AVDD (V) Figure 21. Third-Order IMD Products vs. AVDD @ fOUT = 10 MHz, fDAC = 320 MSPS, fDATA = 160 MSPS Figure 18. Third-Order IMD Products vs. fOUT and Interpolation Rate, 1× fDATA = 160 MSPS, 2× fDATA = 160 MSPS, 4× fDATA = 80 MSPS, 8× fDATA = 50 MSPS 90 3.
AD9773 0 0 –10 –20 –30 AMPLITUDE (dBm) AMPLITUDE (dBm) –20 –40 –50 –60 –70 –40 –60 –80 –80 –90 –100 100 FREQUENCY (MHz) 0 10 15 20 25 30 35 40 FREQUENCY (MHz) Figure 27. Two-Tone IMD Performance, fDATA = 150 MSPS, Interpolation = 4× Figure 24.
0 –10 –20 –20 –30 –30 AMPLITUDE (dBm) 0 –10 –40 –50 –60 –70 –40 –50 –60 –70 –90 –90 –100 –100 0 100 200 300 FREQUENCY (MHz) 0 20 40 60 FREQUENCY (MHz) Figure 31. Eight-Tone IMD Performance, fDATA = 160 MSPS, Interpolation = 8× Figure 30. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 50 MSPS, Interpolation = 8× Rev.
AD9773 TERMINOLOGY Adjacent Channel Power Ratio (ACPR) A ratio, in dBc, between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth.
AD9773 MODE CONTROL (VIA SPI PORT) Table 9.
AD9773 Address 0Ah Bit 7 Bit 6 Bit 5 Bit 4 0Bh QDAC Offset Adjustment Bit 9 QDAC IOFFSET Direction 0 = IOFFSET on IOUTA 1 = IOFFSET on IOUTB QDAC Offset Adjustment Bit 8 QDAC Offset Adjustment Bit 7 QDAC Offset Adjustment Bit 6 0Ch 0Dh 1 2 Bit 3 QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 5 Bit 2 QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 4 Bit 1 QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 3 QDAC Offset Adjustment Bit 1 Bit 0 QDAC Coarse Gain Adjustment QDAC
AD9773 Bit 3: Logic 1 enables zero stuffing mode for interpolation filters. REGISTER DESCRIPTION Address 00h Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an input during the data transfer (Phase 2) of the communications cycle. When set to 1, SPI_SDIO can act as an input or output, depending on Bit 7 of the instruction byte. Bit 6: Logic 0 (default) determines the direction (LSB/MSB first) of the communications and data transfer communications cycles.
AD9773 Address 03h Address 05h, 09h Bit 7: Allows the data rate clock (divided down from the DAC clock) to be output at either the DATACLK pin (Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this bit enables the data rate clock at DATACLK, while a 1 in this bit causes the data rate clock to be output at SPI_SDO. For more information, see the Two-Port Data Input Mode section.
AD9773 FUNCTIONAL DESCRIPTION The AD9773 dual interpolating DAC consists of two data channels that can be operated completely independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9773 capable of 2×, 4×, or 8× interpolation. High speed input and output data rates can be achieved within the limitations shown in Table 14. Table 14.
AD9773 The SPI_SDO and SPI_SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. INSTRUCTION BYTE The instruction byte contains the information shown in Table 15. SPI_SDIO (Pin 54)—Serial Data I/O Table 15. N1 0 0 1 1 N0 0 1 0 1 Data is always written into the AD9773 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register Address 00h.
AD9773 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I6(N) R/W I5(N) I4 I3 I2 I1 I0 SDO D7N D6N D20 D10 D00 D7N D6N D20 D10 D00 02857-033 SCLK Figure 33. Serial Register Interface Timing MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CS I0 I1 I2 I3 I4 I5(N) I6(N) R/W SDO D00 D10 D20 D6N D7N D00 D10 D20 D6N D7N Figure 34.
AD9773 NOTES ON SERIAL PORT OPERATION GAIN CONTROL REGISTERS FINE GAIN DAC 1.2VREF IDAC IOUTB1 REFIO COARSE GAIN DAC 0.1μF The same considerations apply to setting the reset bit in Register Address 00h. All other registers are set to their default values, but the software reset does not affect the bits in Register Address 00h. COARSE GAIN DAC QDAC IOUTA2 IOUTB2 FSADJ1 RSET2 02857-037 OFFSET OFFSET CONTROL DAC GAIN REGISTERS CONTROL REGISTERS FSADJ2 RSET1 Figure 37.
AD9773 5 –0.5 4 1R MODE OFFSET CURRENT (mA) –1.0 2R MODE –1.5 –2.0 3 2R MODE 2 1R MODE 1 –2.5 –3.0 400 600 800 FINE GAIN REGISTER CODE (ASSUMING RSET 1, RSET 2 = 1.9kΩ) 1000 0 200 02857-040 200 400 600 800 1000 COARSE GAIN REGISTER CODE (ASSUMING RSET1, RSET2 = 1.9kΩ) Figure 40. Fine Gain Effect on IFULLSCALE 02857-041 0 0 Figure 41.
AD9773 CLOCK INPUT CONFIGURATIONS The clock inputs to the AD9773 can be driven differentially or single-ended. The internal clock circuitry has supply and ground (CLKVDD, CLKGND) separate from the other supplies on the chip to minimize jitter from internal noise sources. Figure 43 shows the AD9773 driven from a single-ended clock source. The CLK+/CLK− pins form a differential input (CLKIN) so that the statically terminated input must be dcbiased to the midswing voltage level of the clock driven input.
AD9773 CLK+ PLLVDD PLL_LOCK 1 = LOCK 0 = NO LOCK AD9773 INTERPOLATION FILTERS, MODULATORS, AND DACS 2 4 However, maximum rates of less than 160 MSPS and all minimum fDATA rates are due to the maximum and minimum speeds of the internal PLL VCO. Figure 48 shows typical performance of the PLL lock signal (Pin 8 or Pin 53) when the PLL is in the process of locking. CLK– PHASE DETECTOR CHARGE PUMP Table 16.
AD9773 76.0 4×, (MOD. ON) 8×, (MOD. ON) 75.5 2×, (MOD. ON) IAVDD (mA) 75.0 74.5 4× 8× 74.0 73.5 2× 73.0 1× 02857-048 72.5 0 50 100 Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking (Typical Lock Time) 35 8× 30 4× 2×, (MOD. ON) 4×, (MOD. ON) 4× 2× 200 150 1× 0 100 150 50 100 150 200 fDATA (MHz) Figure 51. ICLKVDD vs. fDATA vs. Interpolation Rate, PLL Disabled SLEEP/POWER-DOWN MODES (Control Register 00h, Bit 3 and Bit 4) 200 fDATA (MHz) Figure 49. IDVDD vs.
AD9773 TWO-PORT DATA INPUT MODE ONE-PORT/TWO-PORT INPUT MODES The digital data input ports can be configured as two independent ports or as a single (one-port mode) port. In the two-port mode, data at the two input ports is latched into the AD9773 on every rising edge of the data rate clock (DATACLK). Also, in the two-port mode, the AD9773 can be programmed to generate an externally available DATACLK for the purpose of data synchronization.
AD9773 DATACLK INVERSION PLL ENABLED, ONE-PORT MODE (Control Register 02h, Bit 4) (Control Register 02h, Bits [6:1] and 04h, Bits [7:1] By programming this bit, the DATACLK signal shown in Figure 52 can be inverted. With inversion enabled, tOD refers to the time between the rising edge of CLKIN and the falling edge of DATACLK. No other effect on timing occurs. In one-port mode, the I and Q channels receive their data from an interleaved stream at Digital Input Port 1.
AD9773 ONEPORTCLK DRIVER STRENGTH PLL DISABLED, TWO-PORT MODE The drive capability of ONEPORTCLK is identical to that of DATACLK in the two-port mode. Refer to Figure 53 for performance under load conditions. With the PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal clock dividers in the AD9773 synthesize the DATACLK signal at Pin 8, which runs at the input data rate and can be used to synchronize the input data.
AD9773 One-port mode is very useful when interfacing with devices such as the Analog Devices AD6622 or AD6623 transmit signal processors, in which two digital data channels have been interleaved (multiplexed). AMPLITUDE MODULATION Given two sine waves at the same frequency, but with a 90° phase difference, a point of view in time can be taken such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal.
AD9773 MODULATION, NO INTERPOLATION With Control Register 01h, Bit 7 and Bit 6 set to 00, the interpolation function on the AD9773 is disabled. Figure 59 to Figure 62 show the DAC output spectral characteristics of the AD9773 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 01h, Bits 5 and 4. The tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth.
AD9773 MODULATION, INTERPOLATION = 2× With Control Register 01h, Bit 7 and Bit 6 set to 01, the interpolation rate of the AD9773 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, −1). Figure 63 to Figure 66 represent the spectral response of the AD9773 DAC output with 2× interpolation in the various modulation modes to a narrow band baseband signal (again, the tall rectangles in the graphic).
AD9773 MODULATION, INTERPOLATION = 4× With Control Register 01h, Bit 7 and Bit 6 set to 10, the interpolation rate of the AD9773 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, −1). Figure 67 to Figure 70 represent the spectral response of the AD9773 DAC output with 4× interpolation in the various modulation modes to a narrow band baseband signal.
AD9773 MODULATION, INTERPOLATION = 8× With Control Register 01h, Bit 7 and Bit 6 set to 11, the interpolation rate of the AD9773 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +0.707, +1, +0.707, 0, −0.707, −1, +0.707). Figure 71 to Figure 74 represent the spectral response of the AD9773 DAC output with 8× interpolation in the various modulation modes to a narrow band baseband signal.
AD9773 ZERO STUFFING (Control Register 01h, Bit 3) As shown in Figure 75, a 0 or null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (fDAC). This is due to the inherent SIN(x)/x roll-off response in the digitalto-analog conversion. In applications where the desired frequency content is below fDAC/2, this may not be a problem. Note that at fDAC/2, the loss due to SIN(x)/x is 4 dB.
AD9773 INPUT (REAL) OUTPUT (REAL) INPUT (IMAGINARY) OUTPUT INPUT (IMAGINARY) SINωt 90° 90° COSωt 02857-078 INPUT (REAL) Figure 78. Quadrature Modulator e–jωt = COSωt + jSINωt 02857-077 OUTPUT (IMAGINARY) Figure 77.
AD9773 REAL CHANNEL (OUT) A/2 A/2 –fC1 fC –B/2J B/2J – fC fC REAL CHANNEL (IN) A DC COMPLEX MODULATOR TO QUADRATURE MODULATOR IMAGINARY CHANNEL (OUT) –A/2J A/2J – fC –fC IMAGINARY CHANNEL (IN) B DC B/2 B/2 – fC fC A/4 + B/4J A/4 – B/4J A/4 + B/4J –fQ2 –fQ – fC A/4 – B/4J fQ –fQ + fC fQ – fC fQ + fC OUT REAL –A/4 – B/4J A/4 – B/4J A/4 + B/4J –A/4 + B/4J QUADRATURE MODULATOR –fQ IMAGINARY fQ REJECTED IMAGES –fQ 1f C = COMPLEX MODULATION FREQUENCY 2f Q = QUADRATURE MODULATION
AD9773 A system in which multiple baseband signals are complex modulated and then applied to the AD9773 real and imaginary inputs followed by a quadrature modulator is shown in Figure 82, which also describes the transfer function of this system and the spectral output. Note the similarity of the transfer functions given in Figure 82 and Figure 80. Figure 82 adds an additional complex modulator stage for the purpose of summing multiple carriers at the AD9773 inputs.
AD9773 The complex carrier synthesized in the AD9773 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running at fDAC/2. As a result, complex modulation only functions with modulation rates of fDAC/4 and fDAC/8. Regions A and B of Figure 83 to Figure 88 are the result of the complex signal described previously, when complex modulated in the AD9773 by +ejωt.
AD9773 0 0 –20 –20 A B C D A B C –40 –40 –60 –60 –80 –80 D –1.5 –1.0 –0.5 0 0.5 1.0 1.5 –100 –2.0 2.0 –1.5 B –1.0 02857-083 –100 –2.0 A (LO) fOUT (×fDATA) –0.5 A 0 0.5 B 1.0 C 1.5 2.0 (LO) fOUT (×fDATA) Figure 83. 2x Interpolation, Complex fDAC/4 Modulation Figure 86. 2x Interpolation, Complex fDAC/8 Modulation 0 0 –20 –20 A B C D A B C –40 –40 –60 –60 –80 –80 D A –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 02857-084 –100 –4.
0 0 –10 –10 –20 –20 –30 –30 AMPLITUDE (dBm) –40 –50 –60 –70 –50 –60 –70 –90 –100 –100 0 10 20 30 40 FREQUENCY (MHz) 02857-089 –90 0 20 30 40 FREQUENCY (MHz) Figure 91. AD9773 Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 4x, Complex Modulation in AD9773 = +fDAC/4 Figure 89.
0 0 –10 –10 –20 –20 –30 –30 AMPLITUDE (dBm) –40 –50 –60 –70 –50 –60 –70 –90 –100 –100 0 10 20 30 02857-093 –90 40 FREQUENCY (MHz) 0 40 60 80 FREQUENCY (MHz) Figure 95. AD9773 Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 8x, Complex Modulation in AD9773 = +fDAC/8 Figure 93.
AD9773 APPLYING THE OUTPUT CONFIGURATIONS A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage results if IOUTA and/or IOUTB is connected to a load resistor, RLOAD, referred to AGND. This configuration is most suitable for a single-supply system requiring a dc-coupled, ground-referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage.
AD9773 DIFFERENTIAL COUPLING USING AN OP AMP DAC Compliance Voltage/Input Common-Mode Range An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 99. This has the added benefit of providing signal gain as well. In Figure 99, the AD9773 is configured with two equal load resistors, RLOAD, of 25 Ω. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration.
AD9773 EVALUATION BOARD The AD9773 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from Windows 95®, Windows 98®, or Windows NT®/2000. The evaluation board also contains an AD8345 quadrature modulator and support circuitry that allows the user to optimally configure the AD9773 in an image reject transmit signal chain.
AD9773 LECROY TRIG PULSE INP GENERATOR SIGNAL GENERATOR DATACLK INPUT CLOCK AWG2021 OR DG2020 CLK+/CLK– 40-PIN RIBBON CABLE DAC1, DB11–DB0 DAC2, DB11–DB0 AD9773 JUMPER CONFIGURATION FOR TWO-PORT MODE, PLL ON SOLDERED/IN × UNSOLDERED/OUT × × × × × × × × × × × × NOTES 1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED.
AD9773 LECROY TRIG PULSE INP GENERATOR SIGNAL GENERATOR DATACLK INPUT CLOCK AWG2021 OR DG2020 CLK+/CLK– 40-PIN RIBBON CABLE DAC1, DB11–DB0 DAC2, DB11–DB0 AD9773 JUMPER CONFIGURATION FOR TWO-PORT MODE, PLL OFF SOLDERED/IN × UNSOLDERED/OUT × × × × × × × × × × × × NOTES 1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. 2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED.
Figure 105. AD8345 Circuitry on AD9773 Evaluation Board O1P O1N 2 + C72 10V 10μF 02857-105 BCASE VDDM O2P C54 DNP CC0603 C78 0.1μF C75 0.
Figure 106. AD9773 Clock, Power Supplies, and Output Circuitry JP12 CX2 CX1 02857-106 13 12 JP3 IQ JP40 JP27 JP5 C29 0.1μF JP24 JP39 JP25 RC0603 R39 1kΩ JP32 R5 49.9Ω TP14 WHT DVDD; 14 DGND; 7 11 DVDD; 14 DGND; 7 RC0603 R1 200Ω DVDD DVDD DVDD DVDD c + C7 BCASE 10μF 6.3V + C8 10μF 6.3V BCASE + C9 10μF 6.3V BCASE + C10 10μF 6.3V C42 0.1μF CC0603 0.001μF CC0603 C23 0.001μF CC0603 C24 0.001μF CC0603 C25 0.001μF CC0603 C26 CLKN CLKP 0.1μF C11 CC0603 0.
02857-107 RIBBON J1 Rev.
Rev.
02857-109 AD9773 02857-110 Figure 109. AD9773 Evaluation Board Components, Top Side Figure 110. AD9773 Evaluation Board Components, Bottom Side Rev.
02857-111 AD9773 02857-112 Figure 111. AD9773 Evaluation Board Layout, Layer One (Top) Figure 112. AD9773 Evaluation Board Layout, Layer Two (Ground Plane) Rev.
02857-113 AD9773 02857-114 Figure 113. AD9773 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9773 Evaluation Board Layout, Layer Four (Bottom) Rev.
AD9773 OUTLINE DIMENSIONS 14.20 14.00 SQ 13.80 1.20 MAX 0.75 0.60 0.45 12.20 12.00 SQ 11.80 61 61 80 60 1 80 1 60 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) BOTTOM VIEW 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 6.00 BSC SQ 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY (PINS UP) 20 41 40 21 VIEW A 20 41 21 40 0.50 BSC LEAD PITCH 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD 060806-A VIEW A ROTATED 90° CCW ` Figure 115.
AD9773 NOTES Rev.
AD9773 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02857-0-10/07(D) Rev.
