Datasheet

AD9772A
Rev. C | Page 7 of 40
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current
1
−10 +10 µA
Logic 0 Current −10 +10 µA
Input Capacitance 5 pF
CLOCK INPUTS
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
PLL CLOCK ENABLED (SEE Figure 2)
Input Setup Time (t
S
)
T
A
= 25°C 1.5 ns
T
A
= −40 to +85°C 2.1 ns
Input Hold Time (t
H
)
T
A
= 25°C 1.3 ns
T
A
= −40 to +85°C 1.6 ns
Latch Pulse Width (t
LPW
), T
A
= 25°C 1.5 ns
PLL CLOCK DISABLED (SEE Figure 3)
Input Setup Time (t
S
)
T
A
= 25°C −0.7 ns
T
A
= −40 to +85°C −0.4 ns
Input Hold Time (t
H
)
T
A
= 25°C 3.3 ns
T
A
= −40 to +85°C 3.7 ns
Latch Pulse Width (t
LPW
), T
A
= 25°C 1.5 ns
CLK+/CLK− to PLLLOCK Delay (t
OD
)
T
A
= 25°C 1.9 2.8 ns
T
A
= −40 to +85°C 1.8 3.3 ns
PLLLOCK (V
OH
), T
A
= 25°C 3.0 V
PLLLOCK (V
OL
), T
A
= 25°C 0.3 V
1
MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 A.
t
S
0.025%
0.025%
DB0 TO DB13
CLK+ – CLK–
I
OUTA
OR
I
OUTB
t
H
t
LPW
t
PD
t
ST
02253-002
Figure 2. Timing Diagram—PLL Clock Multiplier Enabled
t
S
DB0 TO DB13
0.025%
0.025%
I
OUTA
OR
I
OUTB
t
OD
PLLLOCK
CLK+ – CLK–
t
H
t
LPW
t
PD
t
ST
02253-003
Figure 3. Timing Diagram—PLL Clock Multiplier Disabled