Datasheet

AD9772A
Rev. C | Page 34 of 40
36
34
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
U1
AD9772A
(MSB) DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DVDD
C8
0.1µF
C7
0.1µF
TP14
TP15
RED
BLK
I
OUTA
OUTB
REFLO
C6
1µF
C5
0.1µF
AVDD
RED
TP16
BLK
TP17
WHT
TP5
WHT
TP6
REFIO FSADJ
C4
0.1µF
R10
1.91kΩ
R6
50Ω
TP11
SLEEP WHT
REFLO
INT REF
A
B
1
2
3
JP4
EXT REF
AVDD
CLK–
CLK+
DIV0
DIV1
PLLLOCK
LPF
35
33
R5
VAL
C1
VAL
PLLVDD
NOTE:
SHIELD AROUND R5, C1
CONNECTED TO PLLVDD
c
C9
1µF
C10
0.1µF
CLKVDD
A
B
1
2
3
JP6
A
B
1
2
3
JP5
A
B
1
2
3
JP7
CLKVDD
REDTP7
RESET
TP10
WHT
DB3 DB2 DB1
(LSB) DB0
TP1
WHT
MOD0
c
A
B
1
2
3
JP11
H
L
H
L
A
B
1
2
3
JP10
DVDD
DGND
MOD1
TP2
WHT
C11
0.1µF
C12
1µF
DVDD
TP3
WHT
TP4
WHT
1
2
c
J1
TP28
WHT
c
c
NOTE:
LOCATE ALL DECOUPLING CAPACITORS (C5 TO C12) AS CLOSE AS POSSIBLE TO DUT,
PREFERABLY UNDER DUT ON THE BOTTOM SIGNAL LAYER.
JP8
EDGE
CLOCK
A
B
1
2
3
JP3
SE
DF
DF
CLKVDD
R2
1kΩ
c
R3
1kΩ
C19
0.1µF
A
B
1
2
3
JP2
T1
1
2
3
S
SE
P
6
4
c
JP1
DF
1
2
c
CLOCK
J3
WHT
TP12
A
B
1
2
3
JP9
DF
SE
R1
50Ω
c
T2
3
2
1
S
P
4
6
R17
VAL
R16
VAL
1
2
J6
IOUT
R8
50Ω
C3
10pF
IA
R9
OPT
IB
C2
10pF
R7
50Ω
02253-061
Figure 61. Drafting Schematic of Evaluation Board (Continued)