Datasheet

AD9772A
Rev. C | Page 25 of 40
AD9772A
CLK+
CLKVDD
CLK–
CLKCOM
0.1µF
0.1µF
0.1µF
1kΩ
1kΩ
1kΩ
1kΩ
ECL/PECL
02253-044
The power dissipation is directly proportional to the analog
supply current, I
AVD D
, and the digital supply current, I
DVDD
. I
AVD D
is directly proportional to I
OUTFS
and is not sensitive to f
DATA
.
Conversely, I
DVDD
is dependent on both the digital input
waveform and f
DATA
. Figure 45 shows I
DVDD
as a function of full-
scale sine wave output ratios (f
OUT
/f
DATA
) for various update rates
with DVDD = 3.3 V. The supply current from CLKVDD and
PLLVDD is relatively insensitive to the digital input waveform
but directly proportional to the update rate, as shown in
Figure 46.
Figure 44. Differential Clock Interface
RATIO ( f
OUT
/ f
DATA
)
100
90
40
0
I
DVDD
(mA)
80
70
60
50
0.1 0.2 0.3 0.4 0.5
30
20
10
0
f
DATA
= 160MSPS
f
DATA
= 125MSPS
f
DATA
= 100MSPS
f
DATA
= 65MSPS
f
DATA
= 50MSPS
f
DATA
= 25MSPS
0
2253-045
The quality of the clock and data input signals is important in
achieving the optimum performance. The external clock driver
circuitry should provide the AD9772A with a low jitter clock
input, which meets the minimum/maximum logic levels while
providing fast edges. Although fast clock edges help minimize
jitter manifesting as phase noise on a reconstructed waveform,
the high gain-bandwidth product of the AD9772A differential
comparator can tolerate sine wave inputs as low as 0.5 V p-p,
with minimal degradation in its output noise floor.
Digital signal paths should be kept short, and run lengths
should match to avoid propagation delay mismatch. The
insertion of a low value resistor network (that is, 50 Ω to 200 Ω)
between the AD9772A digital inputs and driver outputs may be
helpful in reducing overshooting and ringing at the digital
inputs that contribute to data feedthrough.
Figure 45. I
DVDD
vs. Ratio @ DVDD = 3.3 V
f
DATA
(MSPS)
25
0
0
CURRENT (mA)
20
15
10
5
50 100 150 200
I
PLLVDD
I
CLKVDD
02253-046
SLEEP MODE OPERATION
The AD9772A has a sleep function that turns off the output current
and reduces the analog supply current to less than 6 mA over the
specified supply range of 3.1 V to 3.5 V. This mode can be activated
by applying a Logic Level 1 to the SLEEP pin. The AD9772A
takes less than 50 ns to power down and then approximately 15 μs
to power up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9772A is dependent on
several factors, including
• The power supply voltages (AVDD, PLLVDD, CLKVDD,
and DVDD)
Figure 46. I
PLLVDD
and I
CLKVDD
vs. f
DATA
• The full-scale current output (I
OUTFS
)
• The update rate (f
DATA
)
• The reconstructed digital input waveform