Datasheet

AD9772A
Rev. C | Page 10 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
SLEEP
LPF
PLLVDD
PLLCOM
CLKVDD
CLKCOM
CLK–
DCOM
DCOM
(MSB) DB13
DB12
DB11
DB10
DB9
NC = NO CONNECT
DB8
DB7
DB6
DB5
CLK+
DIV0
DIV1
RESET
AD9772A
DB4
PLLLOCK
DVDD DVDD AVDD AVDD ACOM I
OUTA
I
OUTB
ACOM FSADJ REFIO REFL
O
ACOM
DB3 DB2 DB1
(LSB) DB0
MOD0 MOD1
DCOM DCOM
DVDD DVDD
NC NC
0
2253-006
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 19, 20 DCOM Digital Common.
3 DB13 Most Significant Data Bit (MSB).
4 to 15 DB12 to DB1 Data Bit 1 to Data Bit 12.
16 DB0 Least Significant Data Bit (LSB).
17 MOD0
Digital High-Pass Filter Response. Active high. This pin invokes the digital high-pass filter response (that is,
half-wave digital mixing mode). Note that quarter-wave digital mixing occurs if this pin and the MOD1 pin
are set high.
18 MOD1
Zero-Stuffing Mode. Active high. This pin invokes zero-stuffing mode. Note that quarter-wave digital mixing
occurs if this pin and the MOD0 pin are set high.
23, 24 NC No Connect. Leave open.
21, 22, 47, 48 DVDD Digital Supply Voltage (3.1 V to 3.5 V).
25 PLLLOCK
Lock Signal of the Phase-Lock Loop. This pin provides the lock signal of the phase-lock loop when the PLL
clock multiplier is enabled, and provides the 1× clock output when the PLL clock multiplier is disabled. High
indicates that PLL is locked to the input clock. The maximum fanout is 1 (that is, <10 pF).
26 RESET
Internal Divider Reset. This pin can reset the internal driver to synchronize the internal 1× clock to the input
data and/or multiple AD9772A devices. The reset is initiated if this pin is momentarily brought high when
PLL is disabled.
27, 28 DIV1, DIV0 PLL Prescaler Divide Ratio. DIV1 and DIV0 set the prescaler divide ratio of the PLL (refer to Table 10).
29 CLK+ Noninverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2).
30 CLK− Inverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2).
31 CLKCOM Clock Input Common.
32 CLKVDD Clock Input Supply Voltage (3.1 V to 3.5 V).
33 PLLCOM Phase-Lock Loop Common.
34 PLLVDD
Phase-Lock Loop (PLL) Supply Voltage (3.1 V to 3.5 V). To disable the PLL clock multiplier, connect PLLVDD to
PLLCOM.
35 LPF
PLL Loop Filter Node. This pin should be left as a no connect (open) unless the DAC update rate is less than
10 MSPS, in which case a series RC should be connected from LPF to PLLVDD as indicated in
Figure 61.
36 SLEEP Power-Down Control Input. Active high. When this pin is not used, connect it to ACOM.
37, 41, 44 ACOM Analog Common.
38 REFLO
Reference Ground When Internal 1.2 V Reference Is Used. Connect this pin to AVDD to disable the internal
reference.