Datasheet

–7–
AN-555
REV. 0
3 4 5 6 7 8 92
RP16
10
1
R1 R9
RCOM
22
INP1 INP2 INP3 INP4 INP5 INP6 INP7 INP8
3 4 5 6 7 8 92
RP9
10
1
R1 R9
RCOM
22
INP9
INP10 INP11 INP12 INP13 INP14
INCK1
3 4 5 6 7 8 92
RP10
10
1
R1 R9
RCOM
22
INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30
3 4 5 6 7 8 92
RP15
10
1
R1 R9
RCOM
22
INP31 INP32 INP33 INP34 INP35 INP36
INCK2
J
CLK
Q
Q
PRE
CLR
U1
12
11
9
7
10
14
DGND;8
DVDD;16
TSSOP112
13
K
1
2
C7
0.1mF
1
2
C8
0.01mF
DVDD
TP29
WHT
TP30
TP31
TP32
DGND;3,4,5
DGND;3,4,5
DGND;3,4,5
DGND;3,4,5
S1
S2
S3
S4
WRT1IN
IQWRT
CLK1IN
IQCLK
CLK2IN
RESET
WRT2IN
IQSEL
1
2
R1
50V
1
2
R2
50V
1
2
R3
50V
1
2
R4
50V
1
2
3
A
B
JP5
JP16
1
2
3
A
B
JP4
1
2
3
A
B
JP3
1
2
3
A
B
DCLKIN1 DCLKIN2
1
3
5
4
15
DGND;8
DVDD;16
TSSOP112
1
2
3
A
B
JP7
JP1
DVDD
1
2
3
A
B
JP6
DVDD
/2 CLOCK DIVIDER
WRT1
CLK1
CLK2
WRT2
TP33
SLEEP
1
2
R13
50V
SLEEP
JP2
2
Q
J
CLK
Q
PRE
U1
CLR
6
K
DVDD
WHT
WHT
WHT
WHT
I
C
IC
I
C
JP9
TP10
B1
BAN-JACK
DVDDIN
L1
BEAD
1
2
C9
10mF
25V
TP37 TP38
TP43
TP39
DGND
DVDD
B2
BAN-JACK
BLKBLKBLK
BLK
RED
TP11
B3
BAN-JACK
AVDDIN
L2
BEAD
1
2
C10
10mF
25V
TP40 TP41
TP44
TP42
AGND
AVDD
B4
BAN-JACK
BLK BLK
BLK
BLK
RED
POWER DECOUPLING AND INPUT CLOCKS
Figure 10. Power Decoupling and Clocks on Dual DAC Evaluation Board