Datasheet
–5–
AN-555
REV. 0
REFIO (C14) may need to be removed under these condi-
tions. Figures 7 and 8 show the internal and external ref-
erence configurations for the AD9709, AD9763, AD9765,
and AD9767.
When using an external reference in this way, the full-
scale output current for each DAC can be defined by;
I
OUT
FS
= 32 ×
V
REF
/R
EXT
Note that in the internal reference configuration, any
additional load on the reference should be buffered with
an external amplifier. This external amplifier is not
included on the evaluation board.
For more detailed information on the operation of the
reference section of the DACs, see page 9 of the data
sheet.
+1.2V REF
AVDD
ACOM
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2kV
0.1mF
ADDITIONAL
EXTERNAL
LOAD
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
I
REF
GAINCTRL
DUAL DAC
REFERENCE
SECTION
Figure 7. Internal Reference Configuration
+1.2V REF
ACOM
CURRENT
SOURCE
ARRAY
AVDD
REFIO
FSADJ
AVDD
2kV
EXTERNAL
REFERENCE
I
REF
GAINCTRL
DUAL DAC
REFERENCE
SECTION
Figure 8. External Reference Configuration
MASTER/SLAVE RESISTOR MODE, GAINCTRL
The AD9709, AD9763, AD9765, AD9767 all allow the gain
of each channel to be independently set by connecting
one R
SET
resistor to FSADJ1 and another R
SET
resistor to
FSADJ2. To add flexibility and reduce system cost, a
single R
SET
resistor can be used to set the gain of both
channels simultaneously.
When GAINCTRL is low (i.e., connected to AGND), the
independent channel gain control mode using two resis-
tors is enabled. In this mode, individual R
SET
resistors
should be connected to FSADJ1 and FSADJ2. When
GAINCTRL is high (i.e., connected to AVDD), the master/
slave channel gain control mode using one resistor is
enabled. In this mode, a single R
SET
resistor is connected
to FSADJ1 and the resistor on FSADJ2 can be removed.
Note: Only parts with date code of 9930 or later have the
Master/Slave GAINCTRL function. For parts prior to this
date code, Pin 42 must be connected to AGND, and the
part will operate in the two resistor, independent gain
control mode.
OUTPUT CONFIGURATION
The AD9709, AD9763, AD9765, AD9767 have been
designed to achieve optimum performance with the
outputs used differentially. A transformer on the evalua-
tion board (Mini-Circuits T1–1T) allows the conversion
of the differential outputs to a single-ended signal. The
bandwidth of this transformer allows low distortion
operation from 350 kHz to well past the Nyquist bandwidth
of the DAC when operating at its highest sampling rate.
Figure 9 shows a typical DAC output configuration. Both
outputs drive a 50 Ω resistor as well as a transformer.
The grounded centertap on the primary of the trans-
former causes the output of the DAC to swing around
ground, allowing for wider p-p swing while still remain-
ing within the output voltage compliance range of the
DAC. On the evaluation board, these resistors are R5,
R6, R7, and R8. This provides a full-scale differential out-
put voltage of 0.67 V p-p when operating with I
OUT
FS =
20 mA and the transformer terminated with 50 Ω.
If the secondary of the transformer is terminated with
50 Ω, the DAC will then be capable of driving 0.5 dBm
into this load at full-scale out.
C4, C5, C6, and C15 (10 pF) on the evaluation board,
working together with the 50 Ω output resistors, form a
low-pass filter which gives some amount of image rejec-
tion at higher output frequencies. In applications where
an amplifier is used in place of the transformer, it is
important that the capacitor values be chosen to limit
the output slew rate of the DAC. If the output of the
amplifier becomes slew rate limited, severe distortion
can result.
AD9709
AD9763
AD9765
AD9767
IOUT
10pF
IOUT
10pF
50V 50V
50V
Figure 9. Typical DAC Output Configuration