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REV. 0

AN-555

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com

GENERAL DESCRIPTION

The AD9709, AD9763, AD9765 and AD9767 are high-

speed, high-performance dual DACs (8-, 10-, 12-, 14-

bits) designed for I/Q transmit applications and for appli-

cations where board space is at a premium. The

evaluation board allows the user to take full advantage

of the various modes in which the AD976x can operate.

This includes operation as dual DACs with their own indi-

vidual digital inputs, as well as interleaved DACs where

data is alternately written from digital input Port 1 to

either of the two DACs. Information on how to operate

the evaluation board is included in this application

note. However, for more detailed performance informa-

tion, the reader should consult the individual data

sheets for the AD9709, AD9763, AD9765, and AD9767.

The 8-, 10-, 12-, and 14-bit DACs in this family are all pin-

for-pin-compatible and are MSB justified. Therefore, the

same evaluation board can be used to evaluate all

four parts.

EVALUATION SETUP

To evaluate the performance of the AD976x dual DAC

family, a small set of measurement and signal genera-

tion equipment is needed. Figure 1 shows a typical test

setup. Power supplies capable of driving from 3 V to 5 V

are needed for both analog and digital circuitry on the

evaluation board. A signal generator and digital word

generator are needed to provide the data and clock

inputs. On the output, an oscilloscope or spectrum

analyzer may be needed, depending on the type of per-

formance being analyzed.

Using the AD9709, AD9763, AD9765, AD9767 Dual DAC Evaluation Board

By Steve Reine and Dawn Ostenberg

CLK

WORD

GENERATOR

DATA IN

DIGITAL

DATA BUS

DUAL DAC

EVALUATION

BOARD

AVDD DVDD

ANALOG

VDD

(3V TO 5V)

DIGITAL

VDD

(3V TO 5V)

ACOM DCOM

CLOCK

SOURCE

OSCILLOSCOPE

SPECTRUM

ANALYZER

DATA

OUT

Figure 1. Typical Test Setup to Evaluate Performance

of AD976x Dual DAC Using Evaluation Board

POWER CONNECTIONS

The AD9709, AD9763, AD9765, AD9767 dual DACs all

have separate digital and analog power and ground

pins. Analog and digital power and ground have their own

banana-style connectors on the dual DAC evaluation

board. The best performance when using the evaluation

board is achieved when analog and digital power and

ground are connected to separate power supplies.

Figure 2 shows the power supply, grounding, and decou-

pling connections for the evaluation board and for the

DAC itself. Note that for best noise rejection on the

power supplies, the high value bulk capacitors are

placed at the external power connectors, while the

smaller value capacitors, needed for high frequency

rejection, are located close to the DAC.

TP10

BAN-JACK

DVDDIN

BEAD

10mF

25V

TP37 TP38

TP43

TP39

DGND

DVDD

BAN-JACK

DVDD1 DVDD2 AVDD

DCOM1

DCOM2

ACOM

0.1mF

0.01mF

0.001mF

DVDD

C11

0.001mF

C12

0.01mF

C13

0.1mF

AVDD

TP11

BAN-JACK

AVDDIN

BEAD

C10

10mF

25V

TP40 TP41

TP44

TP42

AGND

AVDD

BAN-JACK

AD9709

AD9763

AD9765

AD9767

DUAL DAC

Figure 2. Analog and Digital Power Connections on Dual DAC Evaluation Board

Summary of content (12 pages)

PAGE 1
a AN-555 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com Using the AD9709, AD9763, AD9765, AD9767 Dual DAC Evaluation Board By Steve Reine and Dawn Ostenberg GENERAL DESCRIPTION The AD9709, AD9763, AD9765 and AD9767 are highspeed, high-performance dual DACs (8-, 10-, 12-, 14bits) designed for I/Q transmit applications and for applications where board space is at a premium.
PAGE 2
AN-555 Analog and digital supplies can be run at either 3 V or 5 V, and do not have to run from the same supply voltage. Regardless of supply voltage, the digital input data can be safely run from 3 V or 5 V logic levels, as long as the proper resistor packs are placed in the digital input data path (see Digital Inputs section). CLOCK INPUTS SMA connectors S1 to S4 are intended to be used as clock and control lines for the AD976x, and are 50 Ω terminated.
PAGE 3
AN-555 detailed information on the functions of these inputs, as well as the DAC input and output timing, see the AD9709, AD9763, AD9765, and AD9767 data sheets. DUAL DAC MODE Jumper J8 controls the logic level of the MODE pin on the AD976x dual DAC. With this jumper in the D position, the mode pin is pulled to a high logic level and the AD976x is in dual DAC mode.
PAGE 4
AN-555 CLOCK TIMING/PERFORMANCE To ensure that specified setup-and-hold times are met, the digital data inputs should change state on the falling edge of the clock. However, due to timing skews and delays inherent in some circuits, this does not always happen. If the timing of the data transition and the rising edge of the clock violates the setup-and-hold times, SNR performance will be seriously degraded.
PAGE 5
AN-555 enabled. In this mode, a single RSET resistor is connected to FSADJ1 and the resistor on FSADJ2 can be removed. REFIO (C14) may need to be removed under these conditions. Figures 7 and 8 show the internal and external reference configurations for the AD9709, AD9763, AD9765, and AD9767. Note: Only parts with date code of 9930 or later have the Master/Slave GAINCTRL function.
PAGE 6
AN-555 TROUBLESHOOTING The dual DAC evaluation board has been designed to allow optimum performance from the AD9709, AD9763, AD9765, AD9767. However, many factors can contribute to suboptimal performance. The following is a list of potential problems and their likely sources. Problem—Unusually high amount of noise on the output. With an oscilloscope, verify the relative timing between the data transition and the clock input as described in the Clock Timing Performance section.
PAGE 7
AN-555 POWER DECOUPLING AND INPUT CLOCKS B1 RED TP10 DVDDIN BAN-JACK RED TP11 B3 L1 DVDD BEAD 1 BAN-JACK BEAD BAN-JACK C9 10mF BLK TP37 2 25V B2 L2 AVDDIN BLK TP38 BLK TP39 TP43 BLK AVDD 1 C10 10mF BLK TP40 2 25V B4 BAN-JACK DGND BLK TP41 TP44 BLK BLK TP42 AGND JP9 2 1 DCLKIN1 3 DCLKIN2 A B /2 CLOCK DIVIDER JP6 WHT TP29 JP16 WRT1IN S1 IQWRT 2 1 DVDD 3 A B JP2 4 DGND;3,4,5 PRE WHT TP30 3 JP5 CLK1IN S2 IQCLK 2 1 I DGND;3,4,5 WHT TP31 JP1 3 A B C WHT TP3
PAGE 8
AN-555 RP3 R1 R9 RCOM 22 2 3 4 5 6 7 8 9 10 1 INP1 2 P1 P1 1 4 P1 P1 3 6 P1 P1 5 8 P1 P1 7 10 P1 P1 9 12 P1 P1 11 14 P1 P1 13 16 P1 P1 15 18 P1 P1 17 20 P1 P1 19 22 P1 P1 21 24 P1 P1 23 26 P1 P1 25 28 P1 P1 30 P1 P1 29 32 P1 P1 34 P1 P1 33 36 P1 P1 35 38 P1 P1 37 40 P1 P1 27 INP2 INP3 INP4 INP5 INP6 INP7 INP8 INP9 INP10 INP11 INP12 INP13 INP14 DVDD RP5, 10V 1 16 14 2 12 10 16 14 12 2 3 4 5 6 7 8 9 10 1 RP11 R1 R9 RCOM 33
PAGE 9
AN-555 BL1 TP34 WHT NC = 5 3 4 S6 OUT1 DVDD 1 C1 2 VAL 1 1 C2 2 0.01mF C3 ACOM 2 0.1mF MODE1 1 AVDD 1 DB13P1 (MSB) MODE 48 DUTP2 2 DB12P1 AVDD 47 DUTP3 3 DB11P1 IA1 46 DUTP4 4 DB10P1 IB1 45 DUTP5 5 DB9P1 FSADJ1 44 DUTP6 6 DB8P1 REFIO 43 DUTP8 DUTP9 DUTP10 7 DB7P1 DB6P1 FSADJ2 41 9 DB5P1 IA2 40 IB2 U2 DB3P1 AD9763/ ACOM AD9765/ DB2P1 AD9767 SLEEP 1:1 6 T1 JP8 2 3 BL2 1 R5 50V 2 C4 2 10pF 1 R6 C5 2 10pF 1 2 50V TP45 WHT 1 R9 1.
PAGE 10
AN-555 Figure 13. Assembly, Top Side Figure 14. Assembly, Bottom Side –10– REV.
PAGE 11
AN-555 Figure 15. Layer 1, Top Side Figure 16. Layer 2, Ground Plane REV.
PAGE 12
E3661–2–12/99 (rev. 0) AN-555 PRINTED IN U.S.A. Figure 17. Layer 3, Power Plane Figure 18. Layer 4, Bottom Side –12– REV.