Datasheet

AD9754
–9–
REV. A
FUNCTIONAL DESCRIPTION
Figure 16 shows a simplified block diagram of the AD9754. The
AD9754 consists of a large PMOS current source array that is
capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 kΩ).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on a new
architecture that drastically improves distortion performance.
This new switch architecture reduces various timing errors and
provides matching complementary drive signals to the inputs of
the differential current switches.
The analog and digital sections of the AD9754 have separate
power supply inputs (i.e., AVDD and DVDD). The digital sec-
tion, which is capable of operating up to a 125 MSPS clock rate
and over +2.7 V to +5.5 V operating range, consists of edge-
triggered latches and segment decoding logic circuitry. The
analog section, which can operate over a +4.5 V to +5.5 V range
includes the PMOS current sources, the associated differential
switches, a 1.20 V bandgap voltage reference and a reference
control amplifier.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, R
SET
. The external resistor, in combination with
both the reference control amplifier and voltage reference V
REFIO
,
sets the reference current I
REF
, which is mirrored over to the
segmented current sources with the proper scaling factor. The
full-scale current, I
OUTFS
, is 32 times the value of I
REF
.
DAC TRANSFER FUNCTION
The AD9754 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current out-
put, I
OUTFS
, when all bits are high (i.e., DAC CODE = 16383)
while IOUTB, the complementary output, provides no current.
The current output appearing at IOUTA and IOUTB is a func-
tion of both the input code and I
OUTFS
and can be expressed as:
IOUTA = (DAC CODE/16384) × I
OUTFS
(1)
IOUTB = (16383 – DAC CODE)/16384 × I
OUTFS
(2)
where DAC CODE = 0 to 16383 (i.e., Decimal Representation).
As mentioned previously, I
OUTFS
is a function of the reference
current I
REF
, which is nominally set by a reference voltage V
REFIO
and external resistor R
SET
. It can be expressed as:
I
OUTFS
= 32 × I
REF
(3)
where I
REF
= V
REFIO
/R
SET
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
LOAD
, that are tied to analog common, ACOM. Note
that R
LOAD
may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply:
V
OUTA
= IOUTA × R
LOAD
(5)
V
OUTB
= IOUTB × R
LOAD
(6)
Note that the full-scale value of V
OUTA
and V
OUTB
should not
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
The differential voltage, V
DIFF
, appearing across IOUTA and
IOUTB is:
V
DIFF
= (IOUTA – IOUTB) × R
LOAD
(7)
Substituting the values of IOUTA, IOUTB and I
REF
; V
DIFF
can
be expressed as:
V
DIFF
= {(2 DAC CODE – 16383)/16384} ×
V
DIFF
= {(32 R
LOAD
/R
SET
) × V
REFIO
(8)
DIGITAL DATA INPUTS
(
DB13–DB0
)
150pF
+1.20V REF
AVDD ACOM
REFLO
ICOMP
PMOS
CURRENT SOURCE
ARRAY
+5V
SEGMENTED SWITCHES
FOR DB13–DB5
LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
R
SET
2kV
0.1mF
IOUTA
IOUTB
0.1mF
AD9754
SLEEP
LATCHES
I
REF
V
REFIO
CLOCK
I
OUTB
I
OUTA
R
LOAD
50V
V
OUTB
V
OUTA
R
LOAD
50V
V
DIFF
= V
OUTA
– V
OUTB
Figure 16. Functional Block Diagram