Datasheet

REV. B
–4–
AD9753
DIGITAL SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.)
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 2.1 3 V
Logic 0 0 0.9 V
Logic 1 Current –10 +10 µA
Logic 0 Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (t
S
), T
A
= 25°C 1.0 0.5 ns
Input Hold Time (t
H
), T
A
= 25°C 1.0 0.5 ns
Latch Pulsewidth (t
LPW
), T
A
= 25°C 1.5 ns
Input Setup Time (t
S
, PLLVDD = 0 V), T
A
= 25°C –1.0 –1.5 ns
Input Hold Time (t
H
, PLLVDD = 0 V), T
A
= 25°C 2.5 1.7 ns
CLK to PLLLOCK Delay (t
D
, PLLVDD = 0 V), T
A
= 25°C 3.5 4.0 ns
Latch Pulsewidth (t
LPW
PLLVDD = 0 V), T
A
= 25°C 1.5 ns
PLLOCK (V
OH
) 3.0 V
PLLOCK (V
OL
) 0.3 V
CLK INPUTS
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
Min CLK Frequency* 6.25 MHz
*Min CLK Frequency applies only when using internal PLL. When PLL is disabled, there is no minimum CLK frequency.
Specifications subject to change without notice.