Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- GENERAL DESCRIPTION
- PRODUCT HIGHLIGHTS
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- ORDERING GUIDE
- THERMAL CHARACTERISTIC
- PIN CONFIGURATION
- PIN FUNCTION DESCRIPTIONS
- TERMINOLOGY
- Typical Performance Characteristics
- FUNCTIONAL DESCRIPTION
- REFERENCE OPERATION
- REFERENCE CONTROL AMPLIFIER
- PLL CLOCK MULTIPLIER OPERATION
- DAC TIMING WITH PLL ACTIVE
- PLL DISABLED MODE
- INTERLEAVED (2 ) MODE WITH PLL DISABLED
- NONINTERLEAVED MODE WITH PLL DISABLED
- DAC TRANSFER FUNCTION
- ANALOG OUTPUTS
- DIGITAL INPUTS
- INPUT CLOCK AND DATA TIMING RELATIONSHIP
- POWER DISSIPATION
- APPLYING THE AD9753 OUTPUT CONFIGURATIONS
- DIFFERENTIAL COUPLING USING A TRANSFORMER
- DIFFERENTIAL COUPLING USING AN OP AMP
- SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
- SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
- POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION
- APPLICATIONS
- EVALUATION BOARD
- OUTLINE DIMENSIONS
- Revision History
REV. B
AD9753
–23–
S
P
4
6
1
2
3
T2
1
2
1
2
3
JP6
CLK+
A
B
C16
0.1F
P
R9
1k⍀
JP4
DF
J3
CLK
P
1
2
3
JP2
A
B
SE
DF
JP1EDGE
OUT15
CKLVDD
R7
1k⍀
P
1
2
3
JP3
A
B
SE
DF
PGND: 3, 4, 5
P
R8
50⍀
CLK–
C13
10F
10V
TP13
DVDD PLANE
BLK
P
DVDD
J8
L1
FBEAD
1
12
TP14
RED
DGND
J9
1
C14
10F
10V
TP15
AVDD PLANE
BLK
AVDD
J10
L2
FBEAD
1
12
TP16
RED
AGND
J11
1
C15
10F
10V
TP17
CLKVDD
BLK
CLKVDD
J12
L3
FBEAD
1
12
TP11
RED
CLKGND
J13
1
1
2
3
JP7
A
B
PLLVDD PLANE
C1
0.1F
DVDD PLANE
PINS 5, 6
C2
1F
C3
0.1F
C4
1F
PINS 21, 22
C5
0.1F
PINS 41, 44
C6
1F
AVDD PLANE
C7
0.1F
PINS 45, 47
C8
1F
CLKVDD
P
U1 BYPASS CAPS
Figure 35. Evaluation Board Clock Circuitry