Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- GENERAL DESCRIPTION
- PRODUCT HIGHLIGHTS
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- ORDERING GUIDE
- THERMAL CHARACTERISTIC
- PIN CONFIGURATION
- PIN FUNCTION DESCRIPTIONS
- TERMINOLOGY
- Typical Performance Characteristics
- FUNCTIONAL DESCRIPTION
- REFERENCE OPERATION
- REFERENCE CONTROL AMPLIFIER
- PLL CLOCK MULTIPLIER OPERATION
- DAC TIMING WITH PLL ACTIVE
- PLL DISABLED MODE
- INTERLEAVED (2 ) MODE WITH PLL DISABLED
- NONINTERLEAVED MODE WITH PLL DISABLED
- DAC TRANSFER FUNCTION
- ANALOG OUTPUTS
- DIGITAL INPUTS
- INPUT CLOCK AND DATA TIMING RELATIONSHIP
- POWER DISSIPATION
- APPLYING THE AD9753 OUTPUT CONFIGURATIONS
- DIFFERENTIAL COUPLING USING A TRANSFORMER
- DIFFERENTIAL COUPLING USING AN OP AMP
- SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
- SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
- POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION
- APPLICATIONS
- EVALUATION BOARD
- OUTLINE DIMENSIONS
- Revision History

REV.B
–2–
AD9753–SPECIFICATIONS
Parameter Min Typ Max Unit
RESOLUTION 12 Bits
DC ACCURACY
1
Integral Linearity Error (INL) –1.5 ±0.5 +1.5 LSB
Differential Nonlinearity (DNL) –1 ±0.4 +1 LSB
ANALOG OUTPUT
Offset Error –0.025 ±0.01 +0.025 % of FSR
Gain Error (Without Internal Reference) –2 ±0.5 +2 % of FSR
Gain Error (With Internal Reference) –2 ±0.25 +2 % of FSR
Full-Scale Output Current
2
2.0 20.0 mA
Output Compliance Range –1.0 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current
3
100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 MΩ
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
Supply Voltages
AVDD 3.0 3.3 3.6 V
DVDD 3.0 3.3 3.6 V
PLLVDD 3.0 3.3 3.6 V
CLKVDD 3.0 3.3 3.6 V
Analog Supply Current (I
AVDD
)
4
33 36 mA
Digital Supply Current (I
DVDD
)
4
3.5 4.5 mA
PLL Supply Current (I
PLLVDD
)
4
4.5 5.1 mA
Clock Supply Current (I
CLKVDD
)
4
10.0 11.5 mA
Power Dissipation
4
(3 V, I
OUTFS
= 20 mA) 155 165 mW
Power Dissipation
5
(3 V, I
OUTFS
= 20 mA) 216 mW
Power Supply Rejection Ratio
6
—AVDD –1 +1 % of FSR/V
Power Supply Rejection Ratio
6
—DVDD –0.04 +0.04 % of FSR/V
OPERATING RANGE –40 +85 °C
NOTES
1
Measured at I
OUTA
, driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32× the I
REF
current.
3
An external buffer amplifier is recommended to drive any external load.
4
100 MSPS f
DAC
with PLL on, f
OUT
= 1 MHz, all supplies = 3.0 V.
5
300 MSPS f
DAC
.
6
±5% power supply variation.
Specifications subject to change without notice.
DC SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, CLKVDD = 3.3 V, I
OUTFS
= 20 mA, unless
otherwise noted.)