Datasheet

REV. A –3–
AD974
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Units
DIGITAL OUTPUTS
Data Format Serial 16 Bits
Data Coding Straight Binary
V
OL
I
SINK
= 1.6 mA +0.4 +0.4 V
V
OH
I
SOURCE
= 500 µA+4 +4 V
Output Capacitance High-Z State 15 15 pF
Leakage Current High-Z State
V
OUT
= 0 V to V
DIG
±5 ±5 µA
POWER SUPPLIES
Specified Performance
V
DIG
+4.75 +5 +5.25 +4.75 +5 +5.25 V
V
ANA
+4.75 +5 +5.25 +4.75 +5 +5.25 V
I
DIG
4.5 4.5 mA
I
ANA
14 14 mA
Power Dissipation
PWRD LOW 120 120 mW
PWRD HIGH 50 50 µW
TEMPERATURE RANGE
Specified Performance T
MIN
to T
MAX
–40 +85 –40 +85 °C
NOTES
1
LSB means Least Significant Bit. With a ±10 V input, one LSB is 305 µV.
2
Typical rms noise at worst case transitions and temperatures.
3
Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage, and includes the effect
of offset error. For bipolar input, the Full-Scale Error is the worst case of either the –Full-Scale or +Full-Scale code transition voltage errors. For unipolar input
ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage.
4
External 2.5 V reference connected to REF.
5
All specifications in dB are referred to a full-scale ±10 V input.
6
Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB, or 10 bits of accuracy.
7
Recovers to specified performance after a 2 × FS input overvoltage.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Units
Convert Pulsewidth t
1
50 ns
R/C, CS to BUSY Delay t
2
100 ns
BUSY LOW Time t
3
4.0 µs
BUSY Delay after End of Conversion t
4
50 ns
Aperture Delay t
5
40 ns
Conversion Time t
6
3.8 4.0 µs
Acquisition Time t
7
1.0 µs
Throughput Time t
6
+ t
7
5 µs
R/C Low to DATACLK Delay t
8
220 ns
DATACLK Period t
9
220 ns
DATA Valid Setup Time t
10
50 ns
DATA Valid Hold Time t
11
20 ns
EXT. DATACLK Period t
12
66 ns
EXT. DATACLK HIGH t
13
20 ns
EXT. DATACLK LOW t
14
30 ns
R/C, CS to EXT. DATACLK Setup Time t
15
20 t
12
+ 5 ns
R/C to CS Setup Time t
16
10 ns
EXT. DATACLK to SYNC Delay t
17
15 66 ns
EXT. DATACLK to DATA Valid Delay t
18
25 66 ns
CS to EXT. DATACLK Rising Edge Delay t
19
10 ns
Previous DATA Valid after CS, R/C Low t
20
3.5 µs
BUSY to EXT. DATACLK Setup Time t
21
5ns
Final EXT. DATACLK to BUSY Rising Edge t
22
1.7 µs
A0, A1 to WR1, WR2 Setup Time t
23
10 ns
A0, A1 to WR1, WR2 Hold Time t
24
10 ns
WR1, WR2 Pulsewidth t
25
50 ns
Specifications subject to change without notic e.
(f
S
= 200 kHz, V
DIG
= V
ANA
= +5 V, –40ⴗC to +85ⴗC)