Datasheet

AD9748 Data Sheet
Rev. B | Page 20 of 24
C19
CVDD
CVDD
DB8
DB9
DB10
DB
11
CLKB
DB5
DVDD
DB6
DB7
CLK
DB0
DB1
DB2
DB3
DB4
DB13
DB12
IOUT
AVDD
DVDD CVDD
AVDD
DB8
DB9
DB10
DB
1
1
IB
FS
ADJ
CLKB
DB5
DVDD
DB6
DB7
CLK
CVDD
DCOM
DB0
DB1
DB2
DB3
DB4
DCOM1
DB13
ACOM1
A
VDD
ACOM
IA
REFIO
AVDD1
SLEE
P
DB12
CCOM
CMODE
MODE
CMODE
MODE
T1 – 1T
T1
JP8
JP9
4
3
2
1
5
6
AGND: 3, 4, 5
S3
R
11
C13
28
25
17
23
21
22
18
19
27
26
24
20
29
30
31
32
DNP
DNP
C12
C11
C17
C19
C32
R30
R29
U1
AD9748LFCSP
14
5
6
7
8
9
10
1
1
12
1
2
3
4
13
15
16
WHT
TP1
WHT
TP11
JP1
0.1%
R1
R10
WHT
TP3
TP7
WHT
SLEEP
03211-030
0.1µF
0.1µF
0.1
µF
50
Ω
50Ω
10Ω
10k
Ω
0.1µF
2kΩ
Figure 33. Evaluation Board Schematic—Output Signal Conditioning
U4
U4
JP2
AGND: 5
CVDD: 8
4
3
6
CVDD: 8
C35
0.1µF
C20
10µF
16V
S5
AGND: 3, 4, 5
C34
0.1µF
CKEXT
CLK
CLKB
R5
120Ω
R2
120Ω
R6
50Ω
CVDD
AGND: 5
2
1
7
CVDD
03211-031
Figure 34. Evaluation Board Schematic—Clock Input