Datasheet

AD9748 Data Sheet
Rev. B | Page 16 of 24
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single-
ended conversion, as shown in Figure 26. The AD9748 is
configured with two equal load resistors, R
LOAD
, of 25 Ω. The
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp’s distortion
performance by preventing the DAC’s high slewing output from
overloading the op amp’s input.
AD9748
IOUT
A
IOUTB
C
OPT
500Ω
225Ω
225Ω
500Ω
25Ω
25Ω
AD8047
03211-023
Figure 26. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential
op amp circuit using the AD8047 is configured to provide some
additional signal gain. The op amp must operate off a dual
supply because its output is approximately ±1 V. A high speed
amplifier capable of preserving the differential performance
of the AD9748 while meeting other system level objectives (that
is, cost or power) should be selected. The op amp’s differential
gain, gain setting resistor values, and full-scale output swing
capabilities should all be considered when optimizing this circuit.
The differential circuit shown in Figure 27 provides the
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9748 and the op amp, is also used to level shift the
differential output of the AD9748 to midsupply (that is,
AVDD/2). The AD8041 is a suitable op amp for this application.
AD9748
IOUTA
IOUTB
C
OPT
500Ω
225Ω
225Ω
1kΩ25Ω25Ω
AD8041
1kΩ
AVDD
032
1
1-024
Figure 27. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 28 shows the AD9748 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly
terminated 50 Ωc a b l e because the nominal full-scale current,
I
OUTFS
, of 20 mA flows through the equivalent R
LOAD
of 25 Ω.
In this case, R
LOAD
represents the equivalent load resistance seen
by IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching R
LOAD
.
Different values of I
OUTFS
and R
LOAD
can be selected as long as
the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL),
discussed in the Analog Outputs section. For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.
AD9748
IOUTA
IOUTB
50Ω
25Ω
V
OU
T
A
=
0V
T
O
0.5V
I
OUTFS
=
20mA
50Ω
0321
1-025
Figure 28. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 29 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9748 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, minimizing the nonlinear output impedance
effect on the DAC’s INL performance as described in the
Analog Outputs section. Although this single-ended
configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC
update rates can be limited by U1’s slew rate capabilities. U1
provides a negative unipolar output voltage, and its full-scale
output voltage is simply the product of R
FB
and I
OUTFS
. The full-
scale output should be set within U1’s voltage output swing
capabilities by scaling I
OUTFS
and/or R
FB
. An improvement in ac
distortion performance can result with a reduced I
OUTFS
because
U1 is required to sink less signal current.
AD9748
IOUTA
IOUTB
C
OPT
200Ω
U1
V
OUT
= I
OUTFS
× R
FB
I
OUTFS
= 10mA
R
FB
200Ω
03211-026
Figure 29. Unipolar Buffered Voltage Output