Datasheet

AD9748 Data Sheet
Rev. B | Page 14 of 24
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the
relationship between the position of the clock edges and the
time at which the input data changes. The AD9748 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9748 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases. Figure 21 shows the relationship of
SFDR to clock placement with different sample rates. Note that
at the lower sample rates, more tolerance is allowed in clock
placement, while at higher rates, more care must be taken.
50MHz SFDR
20MHz SFDR
CLOCK PLACEMENT (ns)
SFDR (dB)
80
65
70
75
55
60
35
40
45
50
30
0 2 64 8 10 12
03211-018
Figure 21. SFDR vs. Clock Placement @ f
OUT
= 20 MHz and 50 MHz
(f
CLOCK
= 165 MSPS)
Sleep Mode Operation
The AD9748 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over the
specified supply range of 2.7 V to 3.6 V and the temperature range.
This mode can be activated by applying a Logic Level 1 to the
SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9748 remains enabled if this
input is left disconnected. The AD9748 takes less than 50 ns to
power down and approximately 5 µs to power back up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9748 is dependent on
several factors that include the:
• Power supply voltages (AVDD, CLKVDD, and DVDD)
• Full-scale current output (I
OUTFS
)
• Update rate (f
CLOCK
)
• Reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, I
AVDD
, and the digital supply current, I
DVDD
. I
AVD D
is directly proportional to I
OUTFS
, as shown in Figure 22, and is
insensitive to f
CLOCK
.
Conversely, I
DVDD
is dependent on both the digital input
waveform, f
CLOCK
, and digital supply DVDD. Figure 23 shows I
DVDD
as a function of full-scale sine wave output ratios (f
OUT
/f
CLOCK
)
for various update rates with DVDD = 3.3 V.
I
OUTFS
(mA)
35
0
2
I
AVDD
(mA)
30
25
20
15
10
4
6 8 10 12 14 16 18 20
03211-019
Figure 22. I
AVDD
vs. I
OUTFS
RATIO (f
OUT
/f
CLOCK
)
20
0.01 10.1
I
DVDD
(mA)
14
16
18
12
10
8
6
4
2
0
165MSPS
210MSPS
65MSPS
03211-041
125MSPS
Figure 23. I
DVDD
vs. Ratio @ DVDD = 3.3 V
f
CLOCK
(MSPS)
I
CLKVDD
(mA)
11
0
0 15010050 200 250
PECL
DIFF
SE
10
9
8
7
6
5
4
3
2
1
03211-042
Figure 24. I
CLKVDD
vs. f
CLOCK
and Clock Mode