Datasheet

Data Sheet AD9741/AD9743/AD9745/AD9746/AD9747
Rev. A | Page 7 of 28
DIGITAL AND TIMING SPECIFICATIONS
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
FS
= 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 5. AD9741/AD9743/AD9745/AD9746/AD9747
Parameter Min Typ Max Unit
DAC CLOCK INPUTS (CLKP, CLKN)
Differential Peak-to-Peak Voltage 400 800 1600 mV
Single-Ended Peak-to-Peak Voltage 800 mV
Common-Mode Voltage 300 400 500 mV
Input Current
1
μA
Input Frequency 250 MHz
DATA CLOCK OUTPUT (DCO)
Output Voltage High
2.4
V
Output Voltage Low 0.4 V
Output Current 10 mA
DAC Clock to Data Clock Output Delay (t
DCO
) 2.0 2.2 2.8 ns
DATA PORT INPUTS
Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current 1 μA
Data to DAC Clock Setup Time (t
DBS
Dual-Port Mode) 400 ps
Data to DAC Clock Hold Time (t
DBH
Dual-Port Mode) 1200 ps
DAC Clock to Analog Output Data Latency (Dual-Port Mode) 7 Cycles
Data or IQSEL Input to DAC Clock Setup Time (t
DBS
Single-Port Mode) 400 ps
Data or IQSEL Input to DAC Clock Hold Time (t
DBH
Single-Port Mode) 1200 ps
DAC Clock to Analog Output Data Latency (Single-Port Mode) 8 Cycles
SERIAL PERIPHERAL INTERFACE
SCLK Frequency (f
SCLK
) 40 MHz
SCLK Pulse Width High (t
PWH
) 10 ns
SCLK Pulse Width Low (t
PWL
)
10
ns
CSB to SCLK Setup Time (t
S
) 1 ns
CSB to SCLK Hold Time (t
H
) 0 ns
SDIO to SCLK Setup Time (t
DS
) 1 ns
SDIO to SCLK Hold Time (t
DH
) 0 ns
SCLK to SDIO/SDO Data Valid Time (t
DV
) 1 ns
RESET Pulse Width High 10 ns
WAKE-UP TIME AND OUTPUT LATENCY
From DAC Outputs Disabled 200 μs
From Full Device Power-Down 1200 μs
DAC Clock to Analog Output Latency (Dual-Port Mode) 7 Cycles
DAC Clock to Analog Output Latency (Single-Port Mode) 8 Cycles