Datasheet

Data Sheet AD9742
Rev. C | Page 5 of 32
Parameter Min Typ Max Unit
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
f
CLOCK
= 78 MSPS; f
OUT
= 15.0 MHz to 18.2 MHz
0 dBFS Output 65 dBc
−6 dBFS Output 67 dBc
−12 dBFS Output
65
dBc
−18 dBFS Output 63 dBc
1
Measured single-ended into 50 Ω load.
2
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3
Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS
1
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current −10 +10 µA
Logic 0 Current 10 +10 µA
Input Capacitance
5
pF
Input Setup Time (t
S
) 2.0 ns
Input Hold Time (t
H
) 1.5 ns
Latch Pulse Width (t
LPW
) 1.5 ns
CLK INPUTS
2
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
1
Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
2
Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode.
0.1%
0.1%
t
S
t
H
t
PD
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
02912-B-002
t
LPW
t
ST
Figure 2. Timing Diagram