Datasheet

AD9742 Data Sheet
Rev. C | Page 20 of 32
R6
OPT
S2
IOUTA
2
A
B
JP10
1
3
IX
R11
50Ω
C13
OPT
JP8
IOUT
S3
4
5
6
3
2
1
T1
T1-1T
JP9
C12
OPT
R10
50Ω
S1
IOUTB
1
2
3
A B
JP11
IY
1
EXT
2
3
INT
A B
JP5
REF
+
+
C14
10µF
16V
C16
0.1µF
C17
0.1µF
AVDD
DVDD
CKEXT
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD
C15
10µF
16V
C18
0.1µF
C19
0.1µF
CUT
UNDER DUT
JP6
JP4
R5
OPT
DVDD
R4
50Ω
CLOCK
S5
CLOCK
TP1
WHT
DVDD
AVDD
DVDD
R2
10kΩ
JP2
MODE
TP3
WHT
REF
C2
0.1µF
C1
0.1µF
C11
0.1µF
R1
2kΩ
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
U1
AD9742
SLEEP
TP11
WHT
R3
10kΩ
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD
02912-B-038
Figure 39. SOIC Evaluation Board—Output Signal Conditioning