Datasheet
AD9740
Rev. B | Page 8 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC = NO CONNECT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB8
DB7
DB6
DB3
DB4
DB5
(
MSB) DB9
DVDD
DCOM
MODE
IOUTA
RESERVED
AVDD
DB2
DB1
DB0
NC
NC
NC
IOUTB
ACOM
NC
SLEEP
NC REFLO
REFIO
FS ADJ
CLOCK
AD9740
TOP VIEW
(Not to Scale)
02911-003
Figure 3. 28-Lead SOIC and TSSOP Pin Configuration
PIN 1
INDICATOR
NC = NO CONNECT
1DB3
2DB2
3DVDD
4DB1
5DB0
6NC
7NC
8NC
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
9
NC
10
DCOM
11
CLKVDD
12
CLK+
13
CLK
–
14
CLKCOM
15
CMODE
16
MODE
3
2
DB4
3
1
DB5
30
DB6
29
DB7
28
DB8
27
DB9 (MSB)
26
DCOM
25
SLEEP
TOP VIEW
(Not to Scale)
AD9740
02911-004
Figure 4. 32-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
SOIC/TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic Description
1 27 DB9 (MSB) Most Significant Data Bit (MSB).
2 to 9 28 to 32, 1, 2, 4 DB8 to DB1 Data Bits 8 to 1.
10 5 DB0 (LSB) Least Significant Data Bit (LSB).
11 to 14, 19 6 to 9 NC No Internal Connection.
15 25 SLEEP
Power-Down Control Input. Active high. Contains active pull-down circuit; it can be
left unterminated if not used.
16 N/A REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both
internal and external reference operation modes.
17 23 REFIO
Reference Input/Output. Serves as reference input when using external reference.
Serves as 1.2 V reference output when using internal reference. Requires 0.1 μF capacitor
to ACOM when using internal reference.
18 24 FS ADJ Full-Scale Current Output Adjust.
20 19, 22 ACOM Analog Common.
21 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 N/A RESERVED Reserved. Do Not Connect to Common or Supply.
24 17, 18 AVDD Analog Supply Voltage (3.3 V).
25 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
N/A 15 CMODE
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+
and float CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver
(terminations on-chip).
26 10, 26 DCOM Digital Common.
27 3 DVDD Digital Supply Voltage (3.3 V).
28 N/A CLOCK Clock Input. Data latched on positive edge of clock.
N/A 12 CLK+ Differential Clock Input.
N/A 13 CLK− Differential Clock Input.
N/A 11 CLKVDD Clock Supply Voltage (3.3 V).
N/A 14 CLKCOM Clock Common.