Datasheet

AD9740
Rev. B | Page 31 of 32
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12° MAX
1.00
0.85
0.80
SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
0.50
0.40
0.30
3.50 REF
0.50
BSC
PIN 1
INDICATOR
TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ
3.25
3.10 SQ
2.95
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
Figure 58. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9740AR −40°C to +85°C 28-Lead Wide Body SOIC RW-28
AD9740ARRL −40°C to +85°C 28-Lead Wide Body SOIC RW-28
AD9740ARZ
1
−40°C to +85°C 28-Lead Wide Body SOIC RW-28
AD9740ARZRL
1
−40°C to +85°C 28-Lead Wide Body SOIC RW-28
AD9740ARU −40°C to +85°C 28-Lead TSSOP RU-28
AD9740ARURL7 −40°C to +85°C 28-Lead TSSOP RU-28
AD9740ARUZ
1
−40°C to +85°C 28-Lead TSSOP RU-28
AD9740ARUZRL7
1
−40°C to +85°C 28-Lead TSSOP RU-28
AD9740ACP −40°C to +85°C 32-Lead LFCSP CP-32-2
AD9740ACPRL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD9740ACPZ
1
−40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD9740ACPZRL7
1
−40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD9740-EB Evaluation Board (SOIC)
AD9740ACP-PCB Evaluation Board (LFCSP)
1
Z = Pb-free part.