Datasheet

AD9737A/AD9739A Data Sheet
Rev. | Page 62 of 64
Table 29. Recommended SPI Initialization
Step Address (Hex) Write Value Comments
1 0x00 0x00
Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto
Bits[2:0] because the MSB/LSB format can be unknown at power-up.
2 0x00 0x20 Software reset to default SPI values.
3 0x00 0x00 Clear the reset bit.
4 0x22 0x0F Set the common-mode voltage of DACCLK_P and DACCLK_N inputs
5 0x23 0x0F
6 0x24 0x30 Configure the Mu controller.
7 0x25 0x80
8 0x27 0x44
9
0x28
0x6C
10 0x29 0xCB
11 0x26 0x02
12
0x26
0x03
Enable the Mu controller search and track mode.
13 Wait for 160 k × 1/f
DATA
cycles.
14 0x2A
Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop
is locked. If it is not locked, return to Step 10 and repeat. Limit attempts to three before
breaking out of the loop and reporting a Mu lock failure.
15 Ensure that the AD9737A/AD9739A are fed with DCI clock input from the data source.
16
0x13
0x72
Set FINE_DEL_SKEW to 2.
17 0x10 0x00 Disable the data Rx controller before enabling it.
18 0x10 0x02 Enable the data Rx controller for loop and IRQ.
19 0x10 0x03 Enable the data Rx controller for search and track mode.
20 Wait for 135 k × 1/f
DATA
cycles.
21 0x21
Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop
is locked and tracking. If it is not locked and tracking, return to Step 16 and repeat. Limit
attempts to three before breaking out of the loop and reporting an Rx data lock failure.
22
0x06
0x07
0x00
0x02
Optional: modify the TxDAC I
OUTFS
setting (the default is 20 mA).
23 0x08 0x00 Optional: modify the TxDAC operation mode (the default is normal mode).
C