Datasheet

Data Sheet AD9737A/AD9739A
Rev. | Page 5 of 64
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I
OUTFS
= 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-
1996 reduced range link, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
LVDS DATA INPUTS (DB0[13:0], DB1[13:0])
1
Input Common-Mode Voltage Range, V
COM
825 1575 mV
Logic High Differential Input Threshold, V
IH_DTH
175 400 mV
Logic Low Differential Input Threshold, V
IL_DTH
−175 −400 mV
Receiver Differential Input Impedance, R
IN
80
120
Ω
Input Capacitance 1.2 pF
LVDS Input Rate 1250 MSPS
LVDS Minimum Data Valid Period (t
MDE
) (See Figure 159) 344 ps
LVDS CLOCK INPUT (DCI)
2
Input Common-Mode Voltage Range, V
COM
825 1575 mV
Logic High Differential Input Threshold, V
IH_DTH
175 400 mV
Logic Low Differential Input Threshold, V
IL_DTH
−175 −400 mV
Receiver Differential Input Impedance, R
IN
80 120 Ω
Input Capacitance 1.2 pF
Maximum Clock Rate 625 MHz
LVDS CLOCK OUTPUT (DCO)
3
Output Voltage High (DCO_P or DCO_N) 1375 mV
Output Voltage Low (DCO_P or DCO_N) 1025 mV
Output Differential Voltage, |V
OD
| 150 200 250 mV
Output Offset Voltage, V
OS
1150 1250 mV
Output Impedance, Single-Ended, R
O
80 100 120 Ω
R
O
Single-Ended Mismatch
10
%
Maximum Clock Rate 625 MHz
1
DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.
2
DCI_P and DCI_N pins.
3
DCO_P and DCO_N pins with 100 Ω differential termination.
C