Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) CSPBGA 160

11-/14-Bit, 2.5 GSPS,

RF Digital-to-Analog Converters

Data Sheet

AD9737A/AD9739A

Rev.

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Direct RF synthesis at 2.5 GSPS update rate

DC to 1.25 GHz in baseband mode

1.25 GHz to 3.0 GHz in mix-mode

Industry leading single/multicarrier IF or RF synthesis

Dual-port LVDS data interface

Up to 1.25 GSPS operation

Source synchronous DDR clocking

Pin compatible with the AD9739

Programmable output current: 8.7 mA to 31.7 mA

Low power: 1.1 W at 2.5 GSPS

APPLICATIONS

Broadband communications systems

DOCSIS CMTS systems

Military jammers

Instrumentation, automatic test equipment

Radar, avionics

FUNCTIONAL BLOCK DIAGRAM

LVDS DDR

RECEIVER

DCI

SDO

SDIO

SCLK

DACCLK

DCO

DB0[13:0]DB1[13:0]

CLK DISTRIBUTION

(DIV-BY-4)

DATA

CONTROLLER

4-TO-1

DATA ASSEMBLER

SPI

RESET

DLL

(MU CONTROLLER)

LVDS DDR

RECEIVER

DATA

LATCH

IOUTN

IOUTP

VREF

I120

IRQ

1.2V

DAC BIAS

AD9737A/AD9739A

TxDAC

CORE

09616-001

Figure 1.

GENERAL DESCRIPTION

The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high

performance RF DACs that are capable of synthesizing wideband

signals from dc up to 3 GHz. The AD9737A/AD9739A are pin

and functionally compatible with the AD9739 with the

exception that the AD9737A/AD9739A do not support

synchronization or RZ mode, and are specified to operate

between 1.6 GSPS and 2.5 GSPS.

By elimination of the synchronization circuitry, some nonideal

artifacts such as images and discrete clock spurs remain stationary

on the AD9737A/AD9739A between power-up cycles, thus

allowing for possible system calibration. AC linearity and noise

performance remain the same between the AD9739 and the

AD9737A/AD9739A.

The inclusion of on-chip controllers simplifies system integration.

A dual-port, source synchronous, LVDS interface simplifies the

digital interface with existing FGPA/ASIC technology. On-chip

controllers are used to manage external and internal clock domain

variations over temperature to ensure reliable data transfer from

the host to the DAC core. A serial peripheral interface (SPI) is

used for device configuration as well as readback of status

registers.

The AD9737A/AD9739A are manufactured on a 0.18 µm

CMOS process and operate from 1.8 V and 3.3 V supplies.

They are supplied in a 160-ball chip scale ball grid array for

reduced package parasitics.

PRODUCT HIGHLIGHTS

1. Ability to synthesize high quality wideband signals with

bandwidths of up to 1.25 GHz in the first or second

Nyquist zone.

2. A proprietary quad-switch DAC architecture provides

exceptional ac linearity performance while enabling mix-

mode operation.

3. A dual-port, double data rate, LVDS interface supports the

maximum conversion rate of 2500 MSPS.

4. On-chip controllers manage external and internal clock

domain skews.

5. Programmable differential current output with an 8.66 mA

to 31.66 mA range.

Summary of content (64 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ AD9737A/AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF DCO DATA LATCH CLK DISTRIBUTION (DIV-BY-4) IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK 09616-001 DB1[13:0] Broadband communications systems DOCSIS CMTS systems Military jammers Instrumentation, automatic test equipment Radar, avionics 4-TO-1 DATA ASSEMBLER DCI LVDS DDR RECEIVER APPLICATIONS LVDS DDR RECEIVER I120 DB0[13:0] Direct RF synthesis at 2.5 GSPS update rate DC to 1.
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AD9737A/AD9739A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Register Map Description .................................................. 40 Applications ....................................................................................... 1 SPI Operation ............................................................................. 40 Functional Block Diagram .................................................
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Data Sheet AD9737A/AD9739A REVISION HISTORY 2/12—Rev. B to Rev. C Changes to Figure 5........................................................................... 9 Changes to Table 7 ..........................................................................11 Changes to Ordering Guide ...........................................................63 2/12—Rev. A to Rev. B Added AD9737A ................................................................ Universal Reorganized Layout .................................
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AD9737A/AD9739A Data Sheet SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. Table 1.
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Data Sheet AD9737A/AD9739A LVDS DIGITAL SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.31996 reduced range link, unless otherwise noted. Table 2.
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AD9737A/AD9739A Data Sheet SERIAL PORT SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V. Table 3.
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Data Sheet AD9737A/AD9739A AC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA, fDAC = 2400 MSPS, unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE DAC Clock Rate Adjusted DAC Update Rate1 Output Settling Time to 0.1% SPURIOUS-FREE DYNAMIC RANGE (SFDR) fOUT = 100 MHz fOUT = 350 MHz fOUT = 550 MHz fOUT = 950 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), fOUT2 = fOUT1 + 1.
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AD9737A/AD9739A Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter VDDA to VSSA VDD33 to VSS VDD to VSS VDDC to VSSC VSSA to VSS VSSA to VSSC VSS to VSSC DACCLK_P, DACCLK_N to VSSC DCI, DCO to VSS LVDS Data Inputs to VSS IOUTP, IOUTN to VSSA I120, VREF to VSSA IRQ, CS, SCLK, SDO, SDIO, RESET to VSS Junction Temperature Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +1.98 V −0.3 V to +1.98 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.
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Data Sheet AD9737A/AD9739A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 1 13 14 A A B B C C D D E E F F G G AD9737A/AD9739A H 2 3 4 5 6 7 8 9 10 11 12 13 14 AD9737A/AD9739A J J K K L L M M N N P P VDDC, 1.8V, CLOCK SUPPLY VSSA, ANALOG SUPPLY GROUND VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD 09616-002 VDDA, 3.3V, ANALOG SUPPLY VSSC, CLOCK SUPPLY GROUND Figure 4. Digital LVDS Clock Supply Pins (Top View) Figure 2.
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1 2 3 4 5 6 IOUTN Data Sheet IOUTP AD9737A/AD9739A 7 8 9 10 11 12 13 14 A B I120 C VREF D E F IRQ G AD9737A H RESET CS SDIO SCLK SDO J K L M 09616-006 N P Figure 7. AD9737A Analog I/O and SPI Control Pins (Top View) Table 7. AD9737A Pin Function Descriptions Pin No.
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Data Sheet Pin No.
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1 2 3 4 5 6 IOUTP Data Sheet IOUTN AD9737A/AD9739A 7 8 9 10 11 12 13 14 A B I120 C VREF D E F IRQ G AD9739A H RESET CS SDIO SCLK SDO J K L M 09616-037 N P Figure 8. AD9739A Analog I/O and SPI Control Pins (Top View) Table 8. AD9739A Pin Function Descriptions Pin No.
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Data Sheet Pin No.
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AD9737A/AD9739A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS—AD9737A STATIC LINEARITY IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 0.25 0.3 0.20 0.2 0.15 0.10 ERROR (LSB) ERROR (LSB) 0.1 0 –0.1 0.05 0 –0.05 –0.10 –0.2 –0.15 –0.3 0 256 512 768 1024 1280 1536 1792 2048 CODE –0.25 09616-109 –0.4 0 256 512 768 1024 1280 1536 1792 2048 1792 2048 1792 2048 CODE Figure 9. Typical INL, 20 mA at 25°C 09616-112 –0.20 Figure 12.
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Data Sheet AD9737A/AD9739A AC (NORMAL MODE) IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 120 1.2GSPS 100 1.6GSPS 10dB/DIV IIMD (dBc) 80 2.0GSPS 2.4GSPS 60 40 20 200 400 600 800 1000 1200 1400 09616-118 0 1200 09616-119 VBW 20kHz 1200 09616-120 STOP 2.4GHz 09616-115 0 START 20MHz fOUT (MHz) Figure 15. Single Tone Spectrum at fOUT = 91 MHz, fDAC = 2.4 GSPS Figure 18. IMD vs. fOUT over fDAC –150 –152 –154 10dB/DIV NSD (dBm/Hz) –156 –158 1.
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AD9737A/AD9739A Data Sheet fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 90 100 85 95 –6dBFS 80 80 65 75 0dBFS 70 65 50 60 45 55 40 50 45 30 40 0 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 09616-121 35 0 100 200 300 400 500 600 700 800 900 1000 900 1000 900 1000 fOUT (MHz) Figure 21. SFDR vs.
PAGE 17
Data Sheet AD9737A/AD9739A AC (MIX-MODE) fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 90 –150 85 –152 80 –154 +85°C 75 –156 NSD (dBm/Hz) +25°C 65 60 –40°C 55 50 –158 +85°C –160 –162 –164 +25°C 45 –166 40 –168 35 0 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) –170 09616-127 30 0 100 200 300 400 500 600 700 800 900 09616-130 SFDR (dBc) 70 1000 fOUT (MHz) Figure 30. Eight-Tone NSD vs.
PAGE 18
AD9737A/AD9739A Data Sheet fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 100 90 10dB/DIV IMD (dBc) 80 70 60 50 40 STOP 2.4GHz SWEEP 7.174s (601pts) VBW 20kHz 09616-135 30 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 09616-132 START 20MHz #RES BW 20kHz fOUT (MHz) Figure 36. IMD in Mix-Mode vs. fOUT at 2.4 GSPS Figure 33. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.4 GSPS –71.8dBc –69.9dBc –71.9dBc –72.3dBc –68.8dBc –19.5dBm –69.
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Data Sheet AD9737A/AD9739A fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. –65.8dBc –65.8dBc –65.7dBc –65.8dBc –65.6dBc –29.2dBm –65.6dBc –65.8dBc –66.0dBc –66.1dBc –66.1dBc –58.0dBc –58.0dBc –58.0dBc –37.4dBm –37.1dBm –58.2dBc –58.2dBc –58.3dBc –57.9dBc –58.0dBc –37.1dBm –36.9dBm –58.1dBc –58.3dBc –45 –60 –55 –70 –65 10dB/DIV 10dB/DIV –80 –75 –85 –95 –90 –100 –110 –105 –120 –115 –130 –125 –140 OFFSET FREQ 5.000MHz 10.00MHz 15.00MHz 20.00MHz 25.
PAGE 20
AD9737A/AD9739A Data Sheet ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –78.4dBc –78.4dBc –79.3dBc –10.2dBm –79.9dBc –79.0dBc –78.7dBc –78.7dBc 1 –40 –40 –50 –50 –60 –60 10dB/DIV –70 –80 –70 –80 –90 –90 5Δ1 –100 –100 2Δ1 –110 3Δ1 –110 4Δ1 MKR 1 2 3 4 5 MODE TRC SCL N 1 f Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) X 200.10MHz 199.50MHz 399.95MHz 599.45MHz 413.25MHz (Δ) (Δ) (Δ) (Δ) Y –10.
PAGE 21
Data Sheet AD9737A/AD9739A FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –30 –40 –17.9dBc 1 –50 –50 –60 –60 –70 10dB/DIV –70 –80 –90 –53.2dBc 0dBc 0.1dBc –73.3dBc –0.6dBc –72.9dBc –73.5dBc –73.7dBc –80 –90 –100 5Δ1 –110 –100 2Δ1 3Δ1 VBW 2kHz START 50MHz #RES BW 20kHz MKR 1 2 3 4 5 MODE TRC SCL N 1 f Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) X 200.10MHz 221.35MHz 431.30MHz 651.70MHz 413.
PAGE 22
AD9737A/AD9739A Data Sheet EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –69.1dBc –69.2dBc –50 –50 –60 –60 –70 –70 –80 –90 3Δ1 –100 –23.3dBc –0.6dBc –0.3dBc –0.2dBc –80 –90 –100 –110 2Δ1 –110 –120 MKR 1 2 3 MODE TRC SCL N 1 f Δ1 1 f (Δ) Δ1 1 f (Δ) X Y 200.10MHz –22.253dBm 235.60MHz (Δ) –66.457dB 431.25MHz (Δ) –55.
PAGE 23
Data Sheet AD9737A/AD9739A 16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.0dBc –0.1dBc –0.2dBc –0.3dBc –26.3dBm –65.2dBc –63.9dBc –64.1dBc –64.1dBc –60 –60 –70 –70 –80 –80 10dB/DIV –50 –90 –100 4Δ1 –110 3Δ1 2Δ1 –120 –120 –130 –130 START 50MHz #RES BW 20kHz MKR 1 2 3 4 MODE TRC SCL N 1 f Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) VBW 2kHz X Y 160.20MHz –26.390dBm 80.75MHz (Δ) –64.811dB 232.
PAGE 24
AD9737A/AD9739A Data Sheet 32-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.1dBc 0.1dBc 1 –60 –60 –70 –70 –80 –80 10dB/DIV –90 –100 4Δ1 –65.6dBc –64.1dBc –64.2dBc –64.1dBc –90 –100 3Δ1 2Δ1 –120 –120 –130 MODE TRC SCL N 1 f Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) X Y 256.15MHz –29.852dBm 94.05MHz (Δ) –61.581dB 243.20MHz (Δ) –61.313dB 356.25MHz (Δ) –48.122dB CENTER 256MHz #RES BW 30kHz STOP 1GHz SWEEP 24.
PAGE 25
Data Sheet AD9737A/AD9739A 64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.1dBc –50 0.1dBc 0.0dBc –0.4dBc –33.4dBm –60.0dBc –58.7dBc –59.0dBc –58.9dBc –50 –70 –80 –80 10dB/DIV –60 –70 –90 2Δ1 –110 –100 –110 3Δ1 –120 –120 –130 –130 START 50MHz #RES BW 20kHz MKR 1 2 3 MODE TRC SCL N 1 f Δ1 1 f (Δ) Δ1 1 f (Δ) CENTER 448MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) VBW 2kHz X Y 448.
PAGE 26
AD9737A/AD9739A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS—AD9739A STATIC LINEARITY 3.0 1.0 2.5 0.5 2.0 1.5 0 ERROR (LSB) ERROR (LSB) 1.0 0.5 0 –0.5 –0.5 –1.0 –1.5 –1.0 –1.5 –2.0 –2.0 –2.5 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE –3.0 0 2048 1.5 0 1.0 –0.5 0.5 ERROR (LSB) 0.5 –1.0 –1.5 0 –0.5 –2.0 –1.0 –2.5 –1.5 –3.0 6144 8192 10,240 12,288 14,336 16,384 CODE –2.0 09616-210 ERROR (LSB) 2.0 4096 8192 10,240 12,288 14,336 16,384 Figure 81.
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Data Sheet AD9737A/AD9739A 2.0 1.0 1.5 0.5 1.0 0 ERROR (LSB) ERROR (LSB) 0.5 0 –0.5 –1.0 –0.5 –1.0 –1.5 –1.5 –2.0 –2.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE 09616-213 –3.0 –3.0 2048 0 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 84. Typical INL, 10 mA at 25°C 09616-217 –2.5 –2.5 Figure 87. Typical DNL, 30 mA at 25°C 1.2 1.0 1.1 0.5 1.0 TOTAL 0.9 0 POWER (W) ERROR (LSB) 0.8 –0.5 –1.0 –1.5 0.7 0.6 0.5 DVDD18 0.4 CLKVDD 0.3 –2.0 0.2 –2.
PAGE 28
AD9737A/AD9739A Data Sheet AC (NORMAL MODE) STOP 2.4GHz VBW 10kHz START 20MHz STOP 2.4GHz VBW 10kHz Figure 89. Single-Tone Spectrum at fOUT = 91 MHz, fDAC = 2.4 GSPS 09616-010 START 20MHz 09616-007 10dB/DIV 10dB/DIV IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. Figure 92. Single-Tone Spectrum at fOUT = 1091 MHz, fDAC = 2.4 GSPS 80 100 1.2GSPS 95 1.6GSPS 75 1.2GSPS 90 70 85 65 80 2.0GSPS IMD (dBc) SFDR (dBc) 75 60 2.4GSPS 55 2.0GSPS 50 1.
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Data Sheet AD9737A/AD9739A fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 110 90 100 80 –6dBFS 90 –6dBFS –3dBFS 80 IMD (dBc) SFDR (dBc) 70 60 70 –3dBFS 0dBFS 60 0dBFS 50 50 40 40 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 0 100 200 300 400 500 600 700 800 900 1000 09616-016 100 09616-013 0 1000 09616-017 30 30 fOUT (MHz) Figure 95. SFDR vs. fOUT over Digital Full Scale Figure 98. IMD vs.
PAGE 30
AD9737A/AD9739A Data Sheet fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 110 90 100 80 90 +85°C –40°C 60 70 +25°C 60 +25°C 50 +85°C 80 IMD (dBc) SFDR (dBc) 70 –40°C 50 40 40 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 0 200 300 400 500 600 700 800 900 1000 900 1000 fOUT (MHz) Figure 101. SFDR vs. fOUT over Temperature Figure 104. IMD vs.
PAGE 31
Data Sheet AD9737A/AD9739A AC (MIX-MODE) STOP 2.4GHz SWEEP 28.7s (601pts) VBW 10kHz START 20MHz #RES BW 10kHz VBW 10kHz STOP 2.4GHz SWEEP 28.7s (601pts) 09616-030 START 20MHz #RES BW 10kHz 09616-026 10dB/DIV 10dB/DIV fDAC = 2.4 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. Figure 110. Single-Tone Spectrum in Mix-Mode at fOUT = 1.31 GHz, fDAC = 2.4 GSPS Figure 107. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.
PAGE 32
AD9737A/AD9739A Data Sheet FREQ VBW 300kHz FREQ REF RMS RESULTS OFFSET BW CARRIER POWER (MHz) 5 –24.4dBm/ 10 3.84MHz 15 20 25 CENTER 2.81271GHz #RES BW 30kHz SPAN 53.84MHz SWEEP 174.6ms (601pts) (MHz) 3.84 3.84 3.84 3.84 3.84 LOWER (dBc) (dBm) –64.90 –89.30 –66.27 –90.67 –68.44 –92.84 –70.20 –94.60 –70.85 –95.25 UPPER (dBc) (dBm) –63.82 –88.22 –65.70 –90.10 –66.55 –90.95 –68.95 –93.35 –70.45 –94.85 CARRIER POWER (MHz) 5 –27.98dBm/ 10 3.
PAGE 33
Data Sheet AD9737A/AD9739A ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) fOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –80.7dBc –42 –45 –53 –55 –64 –65 –75 –86 –97 –80.7dBc –80.8dBc –75 –85 –115 MODE TRC SCL N 1 f Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) X 200.00MHz 199.60MHz 400.05MHz 597.65MHz 413.35MHz (Δ) (Δ) (Δ) (Δ) Y –11.476dBm –77.042dB –76.238dB –74.526dB –75.919dB STOP 1GHz SWEEP 24.
PAGE 34
AD9737A/AD9739A Data Sheet FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –53.4dBc 1 –50 –47 –60 –57 –70 –67 –80 –90 –0.5dBc –17.6dBm –73.6dBc –75.4dBc –78.1dBc –79.1dBc –87 –97 –110 –107 5Δ1 4Δ1 3Δ1 2Δ1 –117 MKR 1 2 3 4 5 MODE TRC SCL N 1 f Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) X 200MHz 216.60MHz 400MHz 621.30MHz 413.25MHz (Δ) (Δ) (Δ) (Δ) Y –18.593dBm –73.198dB –73.654dB –71.306dB –68.
PAGE 35
Data Sheet AD9737A/AD9739A EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.0dBc 1 0.0dBc 0.1dBc –0.3dBc –21.9dBm –70.0Bc –69.9dBc –69.7dBc –70.1dBc –37 –50 –47 –60 –57 –70 –67 10dB/DIV 10dB/DIV –40 –80 –90 –77 –87 –97 –100 5Δ1 –110 4Δ1 3Δ1 2Δ1 –107 –117 MKR 1 2 3 4 5 VBW 2kHz MODE TRC SCL X N 1 f 200MHz Δ1 1 f (Δ) 216.60MHz Δ1 1 f (Δ) 400MHz Δ1 1 f (Δ) 621.30MHz Δ1 1 f (Δ) 413.
PAGE 36
AD9737A/AD9739A Data Sheet 16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.0dBc –38 1 –58 –64 –68 –74 –78 –88 –98 –24.8dBm –70.4dBc –69.7dBc –69.7dBc –69.8dBc –84 –94 –114 6Δ1 4Δ1 2Δ1 5Δ1 3Δ1 –124 MKR 1 2 3 4 5 6 MODE TRC SCL N 1 f Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) Δ1 1 f (Δ) VBW 2kHz X 289.70MHz 202.05MHz (Δ) –183.65MHz (Δ) 697.95MHz (Δ) 18.70MHz (Δ) 322.70MHz (Δ) Y –25.335dBm –66.
PAGE 37
Data Sheet AD9737A/AD9739A 32-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.1dBc 1 –0.4dBc –0.1dBc 0.0dBc –29.9dBm –65.4dBc –64.8dBc –64.5dBc –64.4dBc –44 –62 –54 –72 –64 –82 –74 10dB/DIV 10dB/DIV –52 –92 –102 3Δ1 –112 –84 –94 –104 4Δ1 2Δ1 –114 –132 –124 VBW 2kHz CENTER 386MHz #RES BW 30kHz STOP 1GHz SWEEP 24.
PAGE 38
AD9737A/AD9739A Data Sheet 64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.3dBc –61 –72 –71 –82 –81 10dB/DIV –62 –92 –102 3Δ1 –121 –131 MODE TRC SCL N 1 f Δ1 1 f (Δ) Δ1 1 f (Δ) X Y 478.75MHz –33.210dBm 372.10MHz (Δ) –58.746dB 132.70MHz (Δ) –55.165dB –62.3dBc –61.5dBc –61.5dBc –61.4dBc –101 –132 MKR 1 2 3 –32.4dBm –91 –122 VBW 2kHz –0.3dBc –111 2Δ1 START 50MHz #RES BW 20kHz 0.
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Data Sheet AD9737A/AD9739A TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from 0 to full scale. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages.
PAGE 40
AD9737A/AD9739A Data Sheet SERIAL PORT INTERFACE (SPI) REGISTER SPI REGISTER MAP DESCRIPTION SPI OPERATION The AD9737A/AD9739A contain a set of programmable registers, described in Table 10, that are used to configure and monitor various internal parameters.
PAGE 41
Data Sheet AD9737A/AD9739A The AD9737A/AD9739A serial port can support both most significant bit (MSB) first and least significant bit (LSB) first data formats. Figure 153 illustrates how the serial port words are formed for the MSB first and LSB first modes. The bit order is controlled by the LSB/MSB bit (Register 0x00, Bit 6). The default value of Bit 6 is 0, MSB first. When the LSB/MSB bit is set high, the serial port interprets both instruction and data bytes LSB first.
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AD9737A/AD9739A Data Sheet SPI REGISTER MAP Table 10.
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Data Sheet AD9737A/AD9739A Name CROSS_ CNT2 PHS_DET Address 0x23 Bit 7 N/A Bit 6 N/A Bit 5 N/A Bit 4 DIR_N Bit 3 CLKN_ OFFSET[3] Bit 2 CLKN_ OFFSET[2] Bit 1 CLKN_ OFFSET[1] Bit 0 CLKN_ OFFSET[0] Default 0x00 0x24 N/A N/A CMP_BST N/A N/A N/A N/A 0x00 MU_DUTY 0x25 POS/NEG ADJ[5] N/A N/A N/A N/A 0x00 MU_CNT1 MU_CNT2 0x26 0x27 MU_ DUTYAUTO_ EN N/A MUDEL[0] PHS_DET AUTO_EN ADJ[4] Read SET_PHS[3] Gain[1] SET_PHS[2] Gain[0] SET_PHS[1] Enable SET_PHS[0] 0x42 0x40 0x28 0x29 0x
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AD9737A/AD9739A Data Sheet INTERRUPT REQUEST (IRQ) ENABLE/STATUS Table 14.
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Data Sheet AD9737A/AD9739A DATA RECEIVER CONTROLLER_DATA SAMPLE DELAY VALUE Table 19. Data Receiver Controller_Data Sample Delay Value Register (LVDS_REC_CNT2 and LVDS_REC_CNT3) Address (Hex) 0x11 Bit Name SMP_DEL[1:0] Bits [7:6] R/W R/W Default Setting 0x11 0x12 SMP_DEL[9:2] [7:0] R/W 0x25 Description Controller enabled: the 10-bit value (with a maximum of 384) represents the start value for the delay line used by the state machine to sample data.
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AD9737A/AD9739A Data Sheet CLK INPUT COMMON MODE Table 23. CLK Input Common Mode Register (CROSS_CNT1 and CROSS_CNT2) Address (Hex) 0x22 0x23 Bit Name DIR_P CLKP_OFFSET[3:0] Bits 4 [3:0] R/W R/W R/W Default Setting 0x0 0x0000 DIR_N CLKN_OFFSET[3:0] 4 [3:0] R/W R/W 0x0 0x0000 Description DIR_P and DIR_N. 0 = VCM at the DACCLK_P input decreases with the offset value. 1 = VCM at the DACCLK_P input increases with the offset value.
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Data Sheet Address (Hex) 0x2A AD9737A/AD9739A Bit Name Guard[4:0] Bits [4:0] R/W R/W Default Setting 0x01011 MU_LOST 1 R 0x0 MU_LKD 0 R 0x0 R/W R Default Setting 0x24 Description 0x24—AD9739A 0x27 0x27—AD9737A Description Sets a guard band from the beginning and end of the Mu delay line, which the Mu controller does not enter into unless it does not find a valid phase outside the guard band (optimal value is Decimal 11 or 0x0B). 0 = Mu controller has not lost lock.
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AD9737A/AD9739A Data Sheet THEORY OF OPERATION RESET IRQ AD9737A/AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF CLK DISTRIBUTION (DIV-BY-4) DATA LATCH IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK Figure 157. Functional Block Diagram of the AD9737A/AD9739A Rev.
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Data Sheet AD9737A/AD9739A LVDS DATA PORT INTERFACE The AD9737A/AD9739A supports input data rates from 1.6 GSPS to 2.5 GSPS using dual LVDS data ports. The interface is source synchronous and double data rate (DDR) where the host provides an embedded data clock input (DCI) at fDAC/4 with its rising and falling edges aligned with the data transitions. The data format is offset binary; however, twos complement format can be realized by reversing the polarity of the MSB differential trace.
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AD9737A/AD9739A Data Sheet DATA RECEIVER CONTROLLER DCI DDR FF DCI WINDOW PRE FINE DELAY PRE DDR FF DELAY DELAY DCI DELAY PATH DCI DELAY DCI WINDOW POST DDR FF 0 90 DIV-BY-4 180 270 STATE MACHINE/ TRACKING LOOP FINE DELAY POST FDAC SAMPLE DELAY DCI WINDOW SAMPLE SAMPLE DELAY PATH FINE DELAY DELAY DELAY SAMPLE DBx[13:1] DDR FF DDR FF DDR FF DDR FF DATA TO CORE 09616-080 ELASTIC FIFO DCO Figure 160.
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Data Sheet AD9737A/AD9739A LVDS Driver and Receiver Input The AD9737A/AD9739A feature an LVDS-compatible driver and receivers. The LVDS driver output used for the DCO signal includes an equivalent 200 Ω source resistor that limits its nominal output voltage swing to ±200 mV when driving a 100 Ω load. The DCO output driver can be powered down via Register 0x01, Bit 5. An equivalent circuit is shown in Figure 162.
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AD9737A/AD9739A Data Sheet LVDS INPUTS (NO FAIL-SAFE) V COM = (V + V )/2 P N V P,N V V P LVDS RECEIVER 100Ω N GND Example V P 1.4V VN 1.0V V P 14-BIT DATA DIGITAL CIRCUITRY 14-BIT DATA MU DELAY ANALOG CIRCUITRY IOUTP IOUTN PHASE DETECTOR MU DELAY CONTROLLER DAC CLOCK 09616-085 The LVDS receivers include 100 Ω termination resistors, as shown in Figure 163. These receivers meet the IEEE-1596.
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Data Sheet 18 AD9737A/AD9739A band setting of 11 (that is, Register 0x29 = 0xCB) corresponds to 88 LSBs, thus providing sufficient margin. NOM_P1 SLOW_P1 FAST_P1 16 Mu Controller Initialization Description 14 The Mu controller must be initialized and placed into track mode as a first step in the SPI boot sequence. The following steps are required for initialization of the Mu controller.
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AD9737A/AD9739A Data Sheet After the Mu delay value is found that exactly matches the desired Mu phase setting and slope (for example, 6 with a negative slope), the Mu controller goes into track mode. In this mode, the Mu controller makes slight adjustments to the delay value to track any variations between the two clock paths due to temperature, time, and supply variations.
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Data Sheet AD9737A/AD9739A ANALOG INTERFACE CONSIDERATIONS INPUT DATA ANALOG MODES OF OPERATION VDD DACCLK_x CLK VG1 VG2 VG1 LATCHES V 3 G DBx[13:0] VG2 VG3 VG4 IOUTP IOUTN D3 D4 D5 D6 D7 D8 D9 D10 DACCLK_x –D8 D3 D2 FOUR-SWITCH DAC OUTPUT (fS MIX MODE) –D7 D4 D1 D5 –D9 –D6 –D10 t –D5 D6 –D1 –D2 D10 D9 D7 –D4 D8 –D3 Figure 171. Mix-Mode DAC Waveforms Figure 171 shows the DAC waveforms for mix-mode.
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AD9737A/AD9739A Data Sheet CLOCK INPUT CONSIDERATIONS AD9737A/AD9739A VCC VREF VT 50Ω 50Ω 50Ω 50Ω D Q D Q 50Ω 10nF 100Ω DACCLK_P DACCLK_N 10nF 10nF 09616-092 10nF 50Ω ADCLK914 VEE Figure 173. ADCLK914 Interface to the AD9737A/AD9739A CLK Input AD9737A/AD9739A 3.9nH VVCO ADF4350 1nF RFOUTA+ PLL VCO DIV-BY-2N N=0–4 FREF DACCLK_P 100Ω 1nF DACCLK_N RFOUTA– 1.8V p-p RFOUTA+ 09616-093 RFOUTA– Figure 174.
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Data Sheet AD9737A/AD9739A The AD9737A/AD9739A clock receiver features the ability to independently adjust the common-mode level of its inputs over a span of ±100 mV centered about its mid-supply point (that is, VDDC/2), as well as an offset for hysteresis purposes. Figure 175 shows the equivalent input circuit of one of the inputs. ESD diodes are not shown for clarity purposes. It has been found through characterization that the optimum setting is for both inputs to be biased at approximately 0.8 V.
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AD9737A/AD9739A Data Sheet If the AD9737A/AD9739A are programmed for IOUTFS = 20 mA, the peak ac current is 9.375 mA and the peak power delivered to the equivalent load is 2.2 mW (that is, P = I2R). Because the source and load resistance seen by the 1:1 balun are equal, this power is shared equally; therefore, the output load receives 1.1 mW or 0.4 dBm.
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Data Sheet AD9737A/AD9739A The AD9737A/AD9739A are intended to serve high dynamic range applications that require wide signal reconstruction bandwidth (that is, DOCSIS CMTS) and/or high IF/RF signal generation. Optimum ac performance can be realized only if the DAC output is configured for differential (that is, balanced) operation with its output common-mode voltage biased to analog ground. The output network used to interface to the DAC should provide a near 0 Ω dc bias path to analog ground.
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AD9737A/AD9739A Data Sheet 3. NONIDEAL SPECTRAL ARTIFACTS The AD9737A/AD9739A output spectrum contains spectral artifacts that are not part of the original digital input waveform. These nonideal artifacts include harmonics (including alias harmonics), images, and clock spurs. Figure 186 shows a spectral plot of the AD9737A/AD9739A within the first Nyquist zone (that is, dc to fDAC/2) reconstructing a 650 MHz, 0 dBFS sine wave at 2.4 GSPS. Besides the desired fundamental tone at the −7.
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Data Sheet AD9737A/AD9739A LAB EVALUATION OF THE AD9737A/AD9739A RECOMMENDED START-UP SEQUENCE Figure 187 shows a recommended lab setup that was used to characterize the performance of the AD9737A/AD9739A. The DPG2 is a dual port LVDS/CMOS data pattern generator that is available from Analog Devices, Inc., with an up to 1.25 GSPS data rate. The DPG2 directly interfaces to the AD9737A/AD9739A evaluation board via Tyco Z-PACK HM-Zd connectors.
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AD9737A/AD9739A Data Sheet Table 29. Recommended SPI Initialization Step 1 Address (Hex) 0x00 Write Value 0x00 2 3 4 5 6 7 8 9 10 11 12 13 14 0x00 0x00 0x22 0x23 0x24 0x25 0x27 0x28 0x29 0x26 0x26 0x20 0x00 0x0F 0x0F 0x30 0x80 0x44 0x6C 0xCB 0x02 0x03 15 16 17 18 19 20 21 22 23 0x2A 0x13 0x10 0x10 0x10 0x72 0x00 0x02 0x03 0x21 0x06 0x07 0x08 0x00 0x02 0x00 Comments Configure for the 4-wire SPI mode with MSB.
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Data Sheet AD9737A/AD9739A OUTLINE DIMENSIONS 14 13 12 11 10 9 8 7 6 5 4 3 2 A B C D E F G H J K L M N P 10.40 BSC SQ 0.80 BSC BOTTOM VIEW TOP VIEW DETAIL A DETAIL A 0.43 MAX 0.25 MIN 1.40 MAX A1 BALL CORNER 1 SEATING PLANE 1.00 MAX 0.85 MIN 0.55 0.50 0.45 BALL DIAMETER COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1. COPLANARITY 0.12 11-18-2011-A A1 BALL CORNER 12.10 12.00 SQ 11.90 Figure 189.