Datasheet

AD9734/AD9735/AD9736
Rev. A | Page 60 of 72
SP
SP
VSSA
6 5
34 2 1
1
43 6
J2
R4 300Ω
3 15
4
415mV COMMON MODE VOLTAGE
400mV p–p
NOTE: T1, T3, AND T3B ARE INSTALLED, R6 AND R8 = 50Ω, R7 = DNP R17 AND R19 = 20Ω, R161 AND R162 = 0Ω, JUMPER ADDED FROM T1 PIN 3 TO T1 PIN 2 ON THE REV. C EVAL BOARD.
J1 VSSA;3,4,5 SMA200UP
VSSA
T3A T3B
T3
ADTL1–12XX
ETC1–1–13
SP
NC=2
ETC1–1–13 ETC1–1–13
T2
ADT2–1T–1P
4 51
3
PS
NC=2
C35 C36
0.1μF 0.1μF
CC0603CC0603
CC0603 CC0603
CC0603
CC0603CC0603
R20 R21
R3 1kΩ
R6 50Ω
C26 DNP
C27 DNP
C38 1nF
C29 1nF
C28 0.1μF
CLKP CLKN VDDC VSSA
25Ω 25Ω
RC0603 RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603 RC0603
R7
DNP
R17 20Ω
R161 0Ω R162 0Ω
R18 DNP
R19 20Ω
RC0603
R8 50Ω
RC0603
RC0603
AN LVDS SIGNAL MAY BE USED TO DRIVE C35 AND C36 IF R20 AND R21 ARE INCREASED TO 50Ω EACH.
R17 AND R19 CAN BE REMOVED AND T1 REPLACED WITH A 1:1 TRANSFORMER FOR HIGHER OUTPUT AMPLITUDE IF MORE H2 IS ACCEPTABLE (TYPICALLY AT LOWER F
OUT
).
R17 AND R19 PRESENT A MORE REAL LOAD TO THE DAC WHICH IMPROVES H2 PERFORMANCE.
T2 AND T4B ARE NOT POPULATED
T1:MINI-CIRCUITS –3dB: 8-600MHz –1dB: 13-300MHz
THIS CONFIGURATION PROVIDES OPTIMUM AC PERFORMANCE FOR IF SIGNAL GENERATION. TYPICAL SIGNAL LEVELS SHOWN FOR 50Ω LOAD.
VSSA
VSSA
VSSA
VSSA
IN
IP
T3:M/A-COM –1dB: 4.5-1000MHz
SP
6 5
34 2 1
T4B T1
ADT2–1T–1P
4 5
3 1
PS
NC=2
VSSA;3,4,5 SMA200UP
04862–105
T3A IS NOT POPULATED
Figure 107. Clock Input and Analog Output, AD973x Evaluation Board, Rev. F